From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAFBEC43441 for ; Tue, 27 Nov 2018 19:51:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B993208E4 for ; Tue, 27 Nov 2018 19:51:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9B993208E4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726484AbeK1Gul (ORCPT ); Wed, 28 Nov 2018 01:50:41 -0500 Received: from mga01.intel.com ([192.55.52.88]:37190 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725883AbeK1Guk (ORCPT ); Wed, 28 Nov 2018 01:50:40 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2018 11:51:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,287,1539673200"; d="scan'208";a="94866875" Received: from schen9-desk.jf.intel.com (HELO [10.54.74.144]) ([10.54.74.144]) by orsmga006.jf.intel.com with ESMTP; 27 Nov 2018 11:51:41 -0800 Subject: Re: [patch V2 18/28] x86/speculation: Prepare for per task indirect branch speculation control To: "Lendacky, Thomas" , Thomas Gleixner , LKML Cc: "x86@kernel.org" , Peter Zijlstra , Andy Lutomirski , Linus Torvalds , Jiri Kosina , Josh Poimboeuf , Andrea Arcangeli , David Woodhouse , Andi Kleen , Dave Hansen , Casey Schaufler , Asit Mallick , Arjan van de Ven , Jon Masters , Waiman Long , Greg KH , Dave Stewart , Kees Cook References: <20181125183328.318175777@linutronix.de> <20181125185005.176917199@linutronix.de> <7ec59a1a-4caf-24f6-3466-ee1d01594861@amd.com> From: Tim Chen Openpgp: preference=signencrypt Autocrypt: addr=tim.c.chen@linux.intel.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: <7ec59a1a-4caf-24f6-3466-ee1d01594861@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/27/2018 09:25 AM, Lendacky, Thomas wrote: >> --- a/arch/x86/kernel/cpu/bugs.c >> +++ b/arch/x86/kernel/cpu/bugs.c >> @@ -148,6 +148,10 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, >> static_cpu_has(X86_FEATURE_AMD_SSBD)) >> hostval |= ssbd_tif_to_spec_ctrl(ti->flags); >> >> + /* Conditional STIBP enabled? */ >> + if (static_branch_unlikely(&switch_to_cond_stibp)) >> + hostval |= stibp_tif_to_spec_ctrl(ti->flags); >> + >> if (hostval != guestval) { >> msrval = setguest ? guestval : hostval; >> wrmsrl(MSR_IA32_SPEC_CTRL, msrval); >> --- a/arch/x86/kernel/process.c >> +++ b/arch/x86/kernel/process.c >> @@ -406,6 +406,11 @@ static __always_inline void spec_ctrl_up >> if (static_cpu_has(X86_FEATURE_SSBD)) >> msr |= ssbd_tif_to_spec_ctrl(tifn); > > I did some quick testing and found my original logic was flawed. Since > spec_ctrl_update_msr() can now be called for STIBP, an additional check > is needed to set the SSBD MSR bit. > > Both X86_FEATURE_VIRT_SSBD and X86_FEATURE_LS_CFG_SSBD cause > X86_FEATURE_SSBD to be set. Before this patch, spec_ctrl_update_msr() was > only called if X86_FEATURE_SSBD was set and one of the other SSBD features > wasn't set. But now, STIBP can cause spec_ctrl_update_msr() to get called > and cause the SSBD MSR bit to be set when it shouldn't (could result in > a GP fault). > I think it will be cleaner just to fold the msr update into __speculation_ctrl_update to fix this issue. Something like this perhaps. Thanks. Tim --- diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 3f5e351..614ec51 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -398,25 +398,6 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); } -static __always_inline void spec_ctrl_update_msr(unsigned long tifn) -{ - u64 msr = x86_spec_ctrl_base; - - /* - * If X86_FEATURE_SSBD is not set, the SSBD bit is not to be - * touched. - */ - if (static_cpu_has(X86_FEATURE_SSBD)) - msr |= ssbd_tif_to_spec_ctrl(tifn); - - /* Only evaluate if conditional STIBP is enabled */ - if (IS_ENABLED(CONFIG_SMP) && - static_branch_unlikely(&switch_to_cond_stibp)) - msr |= stibp_tif_to_spec_ctrl(tifn); - - wrmsrl(MSR_IA32_SPEC_CTRL, msr); -} - /* * Update the MSRs managing speculation control, during context switch. * @@ -428,6 +409,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, { unsigned long tif_diff = tifp ^ tifn; bool updmsr = false; + u64 msr = x86_spec_ctrl_base; /* * If TIF_SSBD is different, select the proper mitigation @@ -440,8 +422,10 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, amd_set_ssb_virt_state(tifn); else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) amd_set_core_ssb_state(tifn); - else if (static_cpu_has(X86_FEATURE_SSBD)) + else if (static_cpu_has(X86_FEATURE_SSBD)) { updmsr = true; + msr |= ssbd_tif_to_spec_ctrl(tifn); + } } /* @@ -449,11 +433,13 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, * otherwise avoid the MSR write. */ if (IS_ENABLED(CONFIG_SMP) && - static_branch_unlikely(&switch_to_cond_stibp)) + static_branch_unlikely(&switch_to_cond_stibp)) { updmsr |= !!(tif_diff & _TIF_SPEC_IB); + msr |= stibp_tif_to_spec_ctrl(tifn); + } if (updmsr) - spec_ctrl_update_msr(tifn); + wrmsrl(MSR_IA32_SPEC_CTRL, msr); } void speculation_ctrl_update(unsigned long tif)