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Message-ID: <b2880b7b-c50d-9161-4278-615cf66c2094@codethink.co.uk>
Date:   Mon, 3 Oct 2022 10:26:44 +0100
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Subject: Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive
 JH71x0 SoCs
Content-Language: en-GB
To:     Conor Dooley <conor@kernel.org>,
        Hal Feng <hal.feng@linux.starfivetech.com>
Cc:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        linux-kernel@vger.kernel.org
References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com>
 <20220929143225.17907-5-hal.feng@linux.starfivetech.com>
 <YzW60PDwnJ7GeLYK@spud>
From:   Ben Dooks <ben.dooks@codethink.co.uk>
Organization: Codethink Limited.
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On 29/09/2022 16:33, Conor Dooley wrote:
> On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> This cache controller is also used on the StarFive JH7100 and JH7110
>> SoCs.
> 
> Ditto this patch, hopefully [0] will have landed as 6.1 material
> before you get around to an actual v2.
> 
> Thanks,
> Conor
> 
> 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/

Also, the l2 cache is being proprely named the ccache (composable cache)
as it is not necessarily an L2 cache.

-- 
Ben