From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53133C433B4 for ; Fri, 14 May 2021 17:29:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3819161177 for ; Fri, 14 May 2021 17:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231710AbhENRaR (ORCPT ); Fri, 14 May 2021 13:30:17 -0400 Received: from terminus.zytor.com ([198.137.202.136]:55143 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229516AbhENRaM (ORCPT ); Fri, 14 May 2021 13:30:12 -0400 Received: from tazenda.hos.anvin.org ([IPv6:2601:646:8602:8be0:7285:c2ff:fefb:fd4]) (authenticated bits=0) by mail.zytor.com (8.16.1/8.15.2) with ESMTPSA id 14EHSaXc3149327 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NO); Fri, 14 May 2021 10:28:36 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 14EHSaXc3149327 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2021042801; t=1621013318; bh=jSzPdXXc18oxGyRbNuujyb/chXDixgHnSADRJ1xFGAw=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=ZgJnsaf9WvSYOIHTsfdIIHP1/Yhs8t/6zK6uHxzk//1cTlkiwLo8CUGJkRx+roSNj KspkzNOpGlHIKX4POtuFDtmRY/EsUe6IGSI8D25gizCAtst3Z6bmTW/1QcAyeiozB1 /1WEI7OaP7Q/8/lFI163/CzIm+Lgwx1fpUO4dbRQycuSdZOO19PHjpMLVLG/sTpm09 62DgYkR8TbVugGuO7gwMfSSqJmZoaXP++4iMAUAnrsPVbt2apA6PnVqUpB9uw2Sy8A xPVnO8J4VKsw//i9+VRclX+OlLAjDk8IhDtLRXug/ZwviZ5d8SBZvocEUJ5FPGe7GQ 4gOnSv3hPZoGQ== Subject: Re: [PATCH] x86/i8259: Work around buggy legacy PIC To: David Laight , "'Thomas Gleixner'" , Maximilian Luz , Ingo Molnar , Borislav Petkov Cc: Sachi King , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" References: <20210512210459.1983026-1-luzmaximilian@gmail.com> <9b70d8113c084848b8d9293c4428d71b@AcuMS.aculab.com> <87r1i94eg6.ffs@nanos.tec.linutronix.de> From: "H. Peter Anvin" Message-ID: Date: Fri, 14 May 2021 10:28:30 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/14/21 9:12 AM, David Laight wrote: > > A more interesting probe would be: > - Write some value to register 1 - the mask. > - Write 9 to register zero (selects interrupt in service register). > - Read register 0 - should be zero since we aren't in as ISR. > - Read register 1 - should get the mask back. > You can also write 8 to register 0, reads then return the pending interrupts. > Their might be pending interrupts - so that value can't be checked. > > But if reads start returning the last written value you might only > have capacitors on the data bus. What data bus? These things haven't been on a physical parallel bus for ages. > The required initialisation registers are pretty fixed for the PC hardware. > But finding the values requires a bit of work. > > David And you always risk activating new bugs. Since this appears to be a specific platform advertising the wrong answer in firmware, this is better handled as a quirk. -hpa