From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
Date: Mon, 22 Jul 2019 00:36:27 -0700 [thread overview]
Message-ID: <b386ff76-b72d-948b-b41d-7ed9ce3a4400@nvidia.com> (raw)
In-Reply-To: <fc6403e6-0022-f505-8864-70bc047207c9@gmail.com>
On 7/22/19 12:30 AM, Dmitry Osipenko wrote:
> 22.07.2019 10:24, Sowjanya Komatineni пишет:
>> On 7/22/19 12:17 AM, Dmitry Osipenko wrote:
>>> 22.07.2019 10:12, Sowjanya Komatineni пишет:
>>>> On 7/21/19 11:32 PM, Dmitry Osipenko wrote:
>>>>> 22.07.2019 6:17, Sowjanya Komatineni пишет:
>>>>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>>>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>>>>>>
>>>>>>>>> During system suspend entry and exit, CPU source will be switched
>>>>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>>>>>>> the switch.
>>>>>>>>>
>>>>>>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>>>>>>> powers up the CPU with PLLP clock source.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>> ---
>>>>>>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>>>>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>>>>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>>>>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>>>>>>> b/drivers/clk/tegra/clk-super.c
>>>>>>>>> index 39ef31b46df5..d73c587e4853 100644
>>>>>>>>> --- a/drivers/clk/tegra/clk-super.c
>>>>>>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>>>>>>> @@ -28,6 +28,9 @@
>>>>>>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>>>>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>>>>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>>>>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>>>>>>> +
>>>>>>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>>>>>>> {
>>>>>>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>>>>>>> *hw, u8 index)
>>>>>>>>> if (index == mux->div2_index)
>>>>>>>>> index = mux->pllx_index;
>>>>>>>>> }
>>>>>>>>> +
>>>>>>>>> + /*
>>>>>>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>>>>>>> + */
>>>>>>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>>>>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>>>>>>> CCLK_SRC_PLLP_OUT4)))
>>>>>>>>> + tegra_clk_set_pllp_out_cpu(true);
>>>>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>>>>>>> switching from PLLP?
>>>>>>> PLLP may be used for other CPU clusters.
>>>>>> Though to avoid flag and check needed to make sure other CPU is not
>>>>>> using before disabling PLLP branch to CPU.
>>>>>>
>>>>>> But leaving it enabled shouldn't impact much as clock source mux is
>>>>>> after this in design anyway.
>>>>>>
>>>>>> But can add as well if its clear that way.
>>>>> The TRM doc says "The CPU subsystem supports a switch-cluster mode
>>>>> meaning that only one of the clusters can be active at any given time".
>>>>>
>>>>> Given that cluster-switching isn't supported in upstream, I don't think
>>>>> that you need to care about the other cluster at all, at least for now.
>>>>>
>>>>> The cluster-switching implementation in upstream is very complicated
>>>>> because it requires a special "hotplugging" CPU governor, which
>>>>> apparently no other platform needs.
>>>>>
>>>>> [snip]
>>>> This patch enables PLLP branches to CPU for both CPUG & CPULP if they
>>>> use PLLP source.
>>>>
>>>> So, to disable PLLP out CPU when not in use, we still need check for
>>>> other cluster because during resume both LP CPU and G CPU gets restored.
>>>> CPUG runs from PLLP on resume and when it does super clk restore for LP
>>>> CPU which may not be using PLLP, but as both uses same super mux
>>>> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP
>>>> branch to CPU during LP CPU restore looses clock to CPU G as well which
>>>> is running from PLLP.
>>>>
>>>> Will add check and disable PLLP if not in use in next version... this
>>>> need extern flag as well to mark PLLP usage with either of CPU's.
>>> I still don't understand why do you need to care about LP cluster at
>>> all, given that it's always in a power-gated state.
>> cclk_lp is registered thru super clk mux which uses same clk_ops as cclk_g.
>>
>> during restore, cclk_lp also gets restored. So both cclk_lp & cclk_g
>> goes thru same clk_ops
>>
>> In this patch, I marked super flags with TEGRA_CPU_CLK for both cclk_lp
>> & cclk_g.
>>
>> So when cclk_lp restore happens, it goes thru same set_parent clk_ops
>> and as its source is not PLLP, it tries to disable PLLP_OUT_CPU if its
>> disabled without adding check for PLLP being in use by other cluster.
> Ah, okay.
>
>> So either I should not mark cclk_lp as TEGRA_CPU_CLK and mark cclk_g
>> only as TEGRA_CPU_CLK so PLLP out to CPU can be disabled without check
>> if its not the source.
>>
>> OR
>>
>> With TEGRA_CPU_CLK used for both cclk_lp & cclk_g, need to add check if
>> PLLP is in use so during cclk_lp restore it doesnt disable PLLP out to CPU.
>>
>>
>> To simplify without check, will just mark cclk_g super clock flag only
>> as TEGRA_CPU_CLK so PLLP_OUT_CPU enable or disable happens only for CPUG
> Sounds good. Then please add a brief comment to the CPULP, telling why
> it misses the flag, for the record.
Sure, will add comment.
next prev parent reply other threads:[~2019-07-22 7:36 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-21 19:40 [PATCH V6 00/21] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend Sowjanya Komatineni
2019-07-21 20:24 ` Marc Zyngier
2019-07-22 9:54 ` Dmitry Osipenko
2019-07-22 10:13 ` Marc Zyngier
2019-07-22 10:57 ` Dmitry Osipenko
2019-07-22 16:21 ` Sowjanya Komatineni
2019-07-22 18:38 ` Marc Zyngier
2019-07-22 23:35 ` Dmitry Osipenko
2019-07-24 23:09 ` Sowjanya Komatineni
2019-07-26 4:48 ` Dmitry Osipenko
2019-07-25 9:55 ` Peter De Schrijver
2019-07-25 10:05 ` Dmitry Osipenko
2019-07-25 10:33 ` Peter De Schrijver
2019-07-25 10:38 ` Peter De Schrijver
2019-07-25 10:59 ` Dmitry Osipenko
2019-08-02 13:05 ` Peter De Schrijver
2019-08-02 17:35 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 02/21] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-21 22:03 ` Dmitry Osipenko
2019-07-21 22:09 ` Dmitry Osipenko
2019-07-21 22:48 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 03/21] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 04/21] clk: tegra: Save and restore divider rate Sowjanya Komatineni
2019-07-21 22:14 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 05/21] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-21 22:18 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 06/21] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-21 21:44 ` Dmitry Osipenko
2019-07-21 22:47 ` Sowjanya Komatineni
2019-07-21 22:21 ` Dmitry Osipenko
2019-07-22 3:22 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 07/21] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-22 10:12 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 08/21] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-21 21:16 ` Dmitry Osipenko
2019-07-21 22:39 ` Sowjanya Komatineni
2019-07-22 3:17 ` Sowjanya Komatineni
2019-07-22 6:32 ` Dmitry Osipenko
2019-07-22 7:12 ` Sowjanya Komatineni
2019-07-22 7:17 ` Dmitry Osipenko
2019-07-22 7:24 ` Sowjanya Komatineni
2019-07-22 7:30 ` Dmitry Osipenko
2019-07-22 7:36 ` Sowjanya Komatineni [this message]
2019-07-21 19:40 ` [PATCH V6 10/21] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 11/21] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-21 21:32 ` Dmitry Osipenko
2019-07-21 22:42 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 12/21] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-21 21:04 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 13/21] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 14/21] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-21 21:38 ` Dmitry Osipenko
2019-07-21 22:45 ` Sowjanya Komatineni
2019-07-22 6:10 ` Dmitry Osipenko
2019-07-22 6:52 ` Sowjanya Komatineni
2019-07-22 7:09 ` Dmitry Osipenko
2019-07-22 7:12 ` Dmitry Osipenko
2019-08-02 17:51 ` Stephen Boyd
2019-08-02 20:39 ` Sowjanya Komatineni
2019-08-07 21:22 ` Stephen Boyd
2019-07-21 19:40 ` [PATCH V6 15/21] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-23 0:58 ` Dmitry Osipenko
2019-07-23 1:08 ` Dmitry Osipenko
2019-07-23 1:41 ` Dmitry Osipenko
2019-07-23 1:52 ` Dmitry Osipenko
2019-07-23 2:10 ` Dmitry Osipenko
[not found] ` <71a88a9c-a542-557a-0eaa-3c90112dee0e@nvidia.com>
2019-07-23 3:03 ` Dmitry Osipenko
2019-07-23 3:09 ` Sowjanya Komatineni
2019-07-23 3:25 ` Dmitry Osipenko
2019-07-23 3:31 ` Sowjanya Komatineni
2019-07-23 3:43 ` Dmitry Osipenko
2019-07-23 14:27 ` Dmitry Osipenko
2019-07-23 23:39 ` Sowjanya Komatineni
2019-07-24 9:31 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 17/21] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-26 6:30 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 18/21] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 19/21] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 20/21] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-21 19:41 ` [PATCH V6 21/21] arm64: dts: tegra210-p3450: Jetson nano " Sowjanya Komatineni
2019-07-21 22:25 ` Dmitry Osipenko
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