Re: [PATCH 0/2] Update register & interrupt info in am65x DSS

[Aradhya Bhatia <a-bhatia1@ti.com>]

On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>>    dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>>    arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>>   .../devicetree/bindings/display/ti/ti,am65x-dss.yaml   | 10 +++++++---
>>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi               |  6 ++++--
>>   2 files changed, 11 insertions(+), 5 deletions(-)
>>
> 
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
> 
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.

The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.

The patches, thus, can be ignored.


Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.

> 
>  Tomi

Regards
Aradhya Bhatia