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[78.210.255.2]) by smtp.googlemail.com with ESMTPSA id z7sm7544362wme.26.2019.05.17.08.55.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 08:55:21 -0700 (PDT) Subject: Re: [PATCHv1 6/8] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states To: Amit Kucheria , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, andy.gross@linaro.org, David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org References: <8648ba97d49a9f731001e4b36611be9650e37f37.1557486950.git.amit.kucheria@linaro.org> From: Daniel Lezcano Message-ID: Date: Fri, 17 May 2019 17:55:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <8648ba97d49a9f731001e4b36611be9650e37f37.1557486950.git.amit.kucheria@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05/2019 13:29, Amit Kucheria wrote: > Add device bindings for cpuidle states for cpu devices. > > Signed-off-by: Amit Kucheria > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 28 +++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index c761269caf80..b615bcb9e351 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -95,6 +95,7 @@ > compatible = "qcom,kryo"; > reg = <0x0 0x0>; > enable-method = "psci"; > + cpu-idle-states = <&LITTLE_CPU_PD>; It is the same micro architecture, the CPUS differ by their max OPP. Shall we call it really little? I take the opportunity to report the capacity-dmips-mhz attribute is missing. The max capacity computation is not triggered, thus the scheduler see the same capacity for both cluster even if one has less OPP. Adding capacity-dmips-mhz = <1024>; to all CPUs will fix it. > next-level-cache = <&L2_0>; > L2_0: l2-cache { > compatible = "cache"; > @@ -107,6 +108,7 @@ > compatible = "qcom,kryo"; > reg = <0x0 0x1>; > enable-method = "psci"; > + cpu-idle-states = <&LITTLE_CPU_PD>; > next-level-cache = <&L2_0>; > }; > > @@ -115,6 +117,7 @@ > compatible = "qcom,kryo"; > reg = <0x0 0x100>; > enable-method = "psci"; > + cpu-idle-states = <&BIG_CPU_PD>; > next-level-cache = <&L2_1>; > L2_1: l2-cache { > compatible = "cache"; > @@ -127,6 +130,7 @@ > compatible = "qcom,kryo"; > reg = <0x0 0x101>; > enable-method = "psci"; > + cpu-idle-states = <&BIG_CPU_PD>; > next-level-cache = <&L2_1>; > }; > > @@ -151,6 +155,30 @@ > }; > }; > }; > + > + idle-states { > + entry-method="psci"; > + > + LITTLE_CPU_PD: little-power-down { > + compatible = "arm,idle-state"; > + idle-state-name = "standalone-power-collapse"; > + arm,psci-suspend-param = <0x00000004>; > + entry-latency-us = <40>; > + exit-latency-us = <40>; > + min-residency-us = <300>; > + local-timer-stop; > + }; > + > + BIG_CPU_PD: big-power-down { > + compatible = "arm,idle-state"; > + idle-state-name = "standalone-power-collapse"; > + arm,psci-suspend-param = <0x00000004>; > + entry-latency-us = <40>; > + exit-latency-us = <40>; > + min-residency-us = <300>; > + local-timer-stop; > + }; > + }; > }; > > thermal-zones { > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog