Re: [PATCH V2 0/5] Add support to defer core initialization

[Kishon Vijay Abraham I <kishon@ti.com>]

+Tom, Milind

Hi,

On 23/01/20 3:25 PM, Kishon Vijay Abraham I wrote:
> Hi Vidya Sagar,
> 
> On 23/01/20 2:54 pm, Vidya Sagar wrote:
>> Hi Kishon,
>> Apologies for pinging again. Could you please review this series?
>>
>> Thanks,
>> Vidya Sagar
>>
>> On 1/11/2020 5:18 PM, Vidya Sagar wrote:
>>> Hi Kishon,
>>> Could you please review this series?
>>>
>>> Also, this series depends on the following change of yours
>>> http://patchwork.ozlabs.org/patch/1109884/
>>> Whats the plan to get this merged?
> 
> I've posted the endpoint improvements as a separate series
> http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com
> 
> I'd prefer this series gets tested by others. I'm also planning to test
> this series. Sorry for the delay. I'll test review and test this series
> early next week.

I tested this series with DRA7 configured in EP mode. So for the series
itself

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Tom, Can you test this series in Cadence platform?

Lorenzo, Andrew,

How do you want to go about merging this series? This series depends on
[1] which in turn is dependent on two other series. If required, I can
rebase [1] on mainline kernel and remove it's dependencies with the
other series. That way this series and [1] could be merged. And the
other series could be worked later. Kindly let me know.

Thanks
Kishon

[1] ->
https://lore.kernel.org/linux-pci/20191231100331.6316-1-kishon@ti.com/
> 
> Thanks
> Kishon
> 
>>>
>>> Thanks,
>>> Vidya Sagar
>>>
>>> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>>>> EPC/DesignWare core endpoint subsystems assume that the core
>>>> registers are
>>>> available always for SW to initialize. But, that may not be the case
>>>> always.
>>>> For example, Tegra194 hardware has the core running on a clock that
>>>> is derived
>>>> from reference clock that is coming into the endpoint system from host.
>>>> Hence core is made available asynchronously based on when host system
>>>> is going
>>>> for enumeration of devices. To accommodate this kind of hardwares,
>>>> support is
>>>> required to defer the core initialization until the respective
>>>> platform driver
>>>> informs the EPC/DWC endpoint sub-systems that the core is indeed
>>>> available for
>>>> initiaization. This patch series is attempting to add precisely that.
>>>> This series is based on Kishon's patch that adds notification mechanism
>>>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>>>
>>>> Vidya Sagar (5):
>>>>    PCI: endpoint: Add core init notifying feature
>>>>    PCI: dwc: Refactor core initialization code for EP mode
>>>>    PCI: endpoint: Add notification for core init completion
>>>>    PCI: dwc: Add API to notify core initialization completion
>>>>    PCI: pci-epf-test: Add support to defer core initialization
>>>>
>>>>   .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>>>   drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>>>   drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>>>   drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>>>   include/linux/pci-epc.h                       |   2 +
>>>>   include/linux/pci-epf.h                       |   5 +
>>>>   6 files changed, 164 insertions(+), 70 deletions(-)
>>>>