From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A866CA9EC7 for ; Tue, 5 Nov 2019 04:30:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EB12B20818 for ; Tue, 5 Nov 2019 04:30:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="osHdHHG7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730422AbfKEEaY (ORCPT ); Mon, 4 Nov 2019 23:30:24 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:46706 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726640AbfKEEaX (ORCPT ); Mon, 4 Nov 2019 23:30:23 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xA54U86m020708; Mon, 4 Nov 2019 22:30:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572928208; bh=k+Xm46G90D+LUV4sRFTaoSNRP8gbMZVRqUwk2h+V8Mk=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=osHdHHG7bx1sr9CrFpi/hS7cQgMXK5ShmKeydx9nPvBGx6ACSC1EcFZ0xjfLzX1LI fI5TDxtupEgH2tHgoBQVZGknccQ4It+lb4cbA74PiT9H0TxsiFbyCT4aub4whkTwKL kiPDxRgsWBV3z95ch76QhI1wav1nxxbJRjrCATBs= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xA54U87x045944 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Nov 2019 22:30:08 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 4 Nov 2019 22:29:52 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 4 Nov 2019 22:29:53 -0600 Received: from [172.24.145.136] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xA54U49R050727; Mon, 4 Nov 2019 22:30:05 -0600 Subject: Re: [PATCH v2 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver To: "Ramuthevar,Vadivel MuruganX" , , CC: , , , References: <20191030081155.29947-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20191030081155.29947-2-vadivel.muruganx.ramuthevar@linux.intel.com> From: Vignesh Raghavendra Message-ID: Date: Tue, 5 Nov 2019 10:00:40 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191030081155.29947-2-vadivel.muruganx.ramuthevar@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 30/10/19 1:41 PM, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > Add dt-bindings documentation for Cadence-QSPI controller to support > spi based flash memories. > The new driver being added in patch 2/2 is supposed to replace drivers/mtd/spi-nor/cadence-quadspi.c. Therefore the bindings should be exactly same as Documentation/devicetree/bindings/mtd/cadence-quadspi.txt. Otherwise, it breaks DT backward compatibility. There cannot be two different sets of bindings for same HW IP. Therefore please rewrite yaml schema to match existing bindings at Documentation/devicetree/bindings/mtd/cadence-quadspi.txt. And then include a patch dropping older bindings. > Signed-off-by: Ramuthevar Vadivel Murugan > --- > .../devicetree/bindings/spi/cadence,qspi.yaml | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi.yaml > > diff --git a/Documentation/devicetree/bindings/spi/cadence,qspi.yaml b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml > new file mode 100644 > index 000000000000..295501f01e5e > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/spi/cadence,qspi.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence QSPI Flash Controller support > + > +maintainers: > + - Ramuthevar Vadivel Murugan > + > +allOf: > + - $ref: "spi-controller.yaml#" > + > +description: | > + Add support for the Cadence QSPI controller,This controller is > + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver > + has been tested On Intel's LGM SoC. > + > +properties: > + compatible: > + const: cadence,qspi > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clocks-names: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + > +examples: > + - | > + spi@ec000000 { > + compatible = "cadence,qspi"; > + reg = <0xec000000 0x100>; > + clocks = <&cgu0 LGM_CLK_QSPI>, <&cgu0 LGM_GCLK_QSPI>; > + clock-names = "qspi"; > + resets = <&rcu0 0x10 1>; > + reset-names = "qspi"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + flash: flash@1 { > + compatible = "spi-nand", "jedec, spi-nor"; s/"jedec, spi-nor"/"jedec,spi-nor" (i.e no space after comma) > + reg = <1>; > + spi-max-frequency = <10000000>; > + }; > + }; > + > -- Regards Vignesh