From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92073C34045 for ; Tue, 18 Feb 2020 16:27:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6B06922B48 for ; Tue, 18 Feb 2020 16:27:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726719AbgBRQ1X (ORCPT ); Tue, 18 Feb 2020 11:27:23 -0500 Received: from mail-out.m-online.net ([212.18.0.10]:37601 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726486AbgBRQ1W (ORCPT ); Tue, 18 Feb 2020 11:27:22 -0500 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 48MR8R2sQDz1rfcQ; Tue, 18 Feb 2020 17:27:19 +0100 (CET) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 48MR8R1ZxZz1qrnN; Tue, 18 Feb 2020 17:27:19 +0100 (CET) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id AKh25iX5XmKa; Tue, 18 Feb 2020 17:27:17 +0100 (CET) X-Auth-Info: FjyVC0AvfVuJZbbbHCumiarSvEf7DE3eoJ2kZJ3WIXU= Received: from [127.0.0.1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Tue, 18 Feb 2020 17:27:17 +0100 (CET) Subject: Re: [PATCH v2 0/2] Add GPIO level-sensitive interrupt support To: Alexandre Torgue , Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org References: <20200218131218.10789-1-alexandre.torgue@st.com> From: Marek Vasut Message-ID: Date: Tue, 18 Feb 2020 17:25:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.2 MIME-Version: 1.0 In-Reply-To: <20200218131218.10789-1-alexandre.torgue@st.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/18/20 2:12 PM, Alexandre Torgue wrote: > This series adds the possibility to handle gpio interrupts on level. > > GPIO hardware block is directly linked to EXTI block but EXTI handles > external interrupts only on edge. To be able to handle GPIO interrupt on > level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) > is retriggered following interrupt type and gpio line value. > > In exti irq chip, retrigger ops function is added. btw. this might be unrelated, but is it possible to have e.g. gpioC2 set as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux selection") prevents that.