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([2001:b07:6468:f312:5cf9:fc14:deb7:51fc]) by smtp.gmail.com with ESMTPSA id a3sm13510841wmb.7.2020.07.03.09.16.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jul 2020 09:16:03 -0700 (PDT) Subject: Re: [PATCH] KVM: x86: Inject #GP if guest attempts to toggle CR4.LA57 in 64-bit mode To: Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastien Boeuf References: <20200703021714.5549-1-sean.j.christopherson@intel.com> From: Paolo Bonzini Message-ID: Date: Fri, 3 Jul 2020 18:16:03 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200703021714.5549-1-sean.j.christopherson@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/07/20 04:17, Sean Christopherson wrote: > Inject a #GP on MOV CR4 if CR4.LA57 is toggled in 64-bit mode, which is > illegal per Intel's SDM: > > CR4.LA57 > 57-bit linear addresses (bit 12 of CR4) ... blah blah blah ... > This bit cannot be modified in IA-32e mode. > > Note, the pseudocode for MOV CR doesn't call out the fault condition, > which is likely why the check was missed during initial development. > This is arguably an SDM bug and will hopefully be fixed in future > release of the SDM. > > Fixes: fd8cb433734ee ("KVM: MMU: Expose the LA57 feature to VM.") > Cc: stable@vger.kernel.org > Reported-by: Sebastien Boeuf > Signed-off-by: Sean Christopherson > --- > arch/x86/kvm/x86.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 00c88c2f34e4..2bb48896dbdc 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -975,6 +975,8 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) > if (is_long_mode(vcpu)) { > if (!(cr4 & X86_CR4_PAE)) > return 1; > + if ((cr4 ^ old_cr4) & X86_CR4_LA57) > + return 1; > } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) > && ((cr4 ^ old_cr4) & pdptr_bits) > && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, > Queued, thanks. Paolo