From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B08C7EE23 for ; Thu, 8 Jun 2023 13:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236667AbjFHNDD (ORCPT ); Thu, 8 Jun 2023 09:03:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236611AbjFHNC4 (ORCPT ); Thu, 8 Jun 2023 09:02:56 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3645A1707; Thu, 8 Jun 2023 06:02:54 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3589O9ll007584; Thu, 8 Jun 2023 15:02:36 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=ejaaba8UeVacQJUONM9cP7HN8p5aNxGX9BhxAgM9wSo=; b=1CFxNfxJ1wZVeNhvewqeLwZoTmY1mz386EXF4XegWKT9SSqGXbctAuUaYP0nT72tHT45 UFhPe6UE17w3GVPHPye2EakQ0nRUIXl+qTgivJKM+c1z/+j5bdZvjLr2sj28TdJ3/lD7 iU7/kdXR1jmToXjfBH38irl8qAMshc6SKeEVItyL+wbCJ1uxo0v/HRxdstQcto70f4jD d5+s/IdFO0RW83EbFIFQjgKakI50Myq6t8bqxUjSj0bIXGh7RsibV5/WKbDMFS6xqAAA MbiYUuWRPrOea9Ux0Vo63QrEzqlYMDUCYkpheewAA8fH0NyN47TUVQp74oi+wOkFkCs2 9w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3r3cax1e8x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Jun 2023 15:02:36 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AD57C10003B; Thu, 8 Jun 2023 15:02:35 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A57C122F7AE; Thu, 8 Jun 2023 15:02:35 +0200 (CEST) Received: from [10.201.21.93] (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 8 Jun 2023 15:02:35 +0200 Message-ID: Date: Thu, 8 Jun 2023 15:02:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v1 6/8] ARM: dts: stm32: Add pinmux groups for Linux Automation GmbH TAC Content-Language: en-US To: =?UTF-8?Q?Leonard_G=c3=b6hrs?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin CC: , , , , References: <20230607115508.2964574-1-l.goehrs@pengutronix.de> <20230607115508.2964574-6-l.goehrs@pengutronix.de> From: Alexandre TORGUE In-Reply-To: <20230607115508.2964574-6-l.goehrs@pengutronix.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-08_09,2023-06-08_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi On 6/7/23 13:55, Leonard Göhrs wrote: > Add pinmux groups required for the Linux Automation GmbH TAC. > > Signed-off-by: Leonard Göhrs > --- > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 129 +++++++++++++++++++++++ > 1 file changed, 129 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index e86d989dd351d..0c864461ca449 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -6,6 +6,17 @@ > #include > > &pinctrl { > + adc1_ain_pins_a: adc1-ain-0 { > + pins { > + pinmux = , /* ADC1_INP2 */ > + , /* ADC1_INP5 */ > + , /* ADC1_INP9 */ > + , /* ADC1_INP10 */ > + , /* ADC1_INP13 */ > + ; /* ADC1_INP15 */ > + }; > + }; > + > adc1_in6_pins_a: adc1-in6-0 { > pins { > pinmux = ; > @@ -341,6 +352,46 @@ pins1 { > }; > }; > > + ethernet0_rgmii_pins_d: rgmii-1 { xxx_pins_d is already defined for rgmii-3, it should be xxx_pins_e And rgmii-1 is already defined, it should be rgmii-4. Don't forget to update boards files with new pinctrl names in eth node. please rebase on top of stm32-next branch. > + pins1 { > + pinmux = , /* ETH_RGMII_GTX_CLK */ > + , /* ETH_RGMII_TXD0 */ > + , /* ETH_RGMII_TXD1 */ > + , /* ETH_RGMII_TXD2 */ > + , /* ETH_RGMII_TXD3 */ > + ; /* ETH_RGMII_TX_CTL */ > + bias-disable; > + drive-push-pull; > + slew-rate = <2>; > + }; > + pins2 { > + pinmux = , /* ETH_RGMII_RXD0 */ > + , /* ETH_RGMII_RXD1 */ > + , /* ETH_RGMII_RXD2 */ > + , /* ETH_RGMII_RXD3 */ > + , /* ETH_RGMII_RX_CLK */ > + ; /* ETH_RGMII_RX_CTL */ > + bias-disable; > + }; > + }; > + > + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-1 { xxx_pins_d is already defined for rgmii-3, it should be xxx_pins_e rgmii-sleep-1 is already defined, it should be rgmii-sleep-4 > + pins1 { > + pinmux = , /* ETH_RGMII_GTX_CLK */ > + , /* ETH_RGMII_TXD0 */ > + , /* ETH_RGMII_TXD1 */ > + , /* ETH_RGMII_TXD2 */ > + , /* ETH_RGMII_TXD3 */ > + , /* ETH_RGMII_TX_CTL */ > + , /* ETH_RGMII_RXD0 */ > + , /* ETH_RGMII_RXD1 */ > + , /* ETH_RGMII_RXD2 */ > + , /* ETH_RGMII_RXD3 */ > + , /* ETH_RGMII_RX_CLK */ > + ; /* ETH_RGMII_RX_CTL */ > + }; > + }; > + > ethernet0_rmii_pins_a: rmii-0 { > pins1 { > pinmux = , /* ETH1_RMII_TXD0 */ > @@ -1104,6 +1155,20 @@ pins { > }; > }; > > + pwm1_pins_c: pwm1-2 { > + pins { > + pinmux = ; /* TIM1_CH2 */ > + drive-push-pull; > + slew-rate = <0>; > + }; > + }; > + > + pwm1_sleep_pins_c: pwm1-sleep-2 { > + pins { > + pinmux = ; /* TIM1_CH2 */ > + }; > + }; > + > pwm2_pins_a: pwm2-0 { > pins { > pinmux = ; /* TIM2_CH4 */ > @@ -1230,6 +1295,26 @@ pins { > }; > }; > > + pwm8_pins_b: pwm8-1 { > + pins { > + pinmux = , /* TIM8_CH1 */ > + , /* TIM8_CH2 */ > + , /* TIM8_CH3 */ > + ; /* TIM8_CH4 */ > + drive-push-pull; > + slew-rate = <0>; > + }; > + }; > + > + pwm8_sleep_pins_b: pwm8-sleep-1 { > + pins { > + pinmux = , /* TIM8_CH1 */ > + , /* TIM8_CH2 */ > + , /* TIM8_CH3 */ > + ; /* TIM8_CH4 */ > + }; > + }; > + > pwm12_pins_a: pwm12-0 { > pins { > pinmux = ; /* TIM12_CH1 */ > @@ -1925,6 +2010,20 @@ pins2 { > }; > }; > > + spi2_pins_c: spi2-2 { > + pins1 { > + pinmux = , /* SPI2_SCK */ > + ; /* SPI2_MOSI */ > + bias-disable; > + drive-push-pull; > + }; > + > + pins2 { > + pinmux = ; /* SPI2_MISO */ > + bias-pull-down; > + }; > + }; > + > spi4_pins_a: spi4-0 { > pins { > pinmux = , /* SPI4_SCK */ > @@ -1939,6 +2038,21 @@ pins2 { > }; > }; > > + spi5_pins_a: spi5-0 { > + pins1 { > + pinmux = , /* SPI5_SCK */ > + ; /* SPI5_MOSI */ > + bias-disable; > + drive-push-pull; > + slew-rate = <1>; > + }; > + > + pins2 { > + pinmux = ; /* SPI5_MISO */ > + bias-disable; > + }; > + }; > + > stusb1600_pins_a: stusb1600-0 { > pins { > pinmux = ; > @@ -2385,6 +2499,21 @@ pins { > }; > }; > > + usart3_pins_f: usart3-5 { > + pins1 { > + pinmux = , /* USART3_TX */ > + ; /* USART3_RTS */ > + bias-disable; > + drive-push-pull; > + slew-rate = <0>; > + }; > + pins2 { > + pinmux = , /* USART3_RX */ > + ; /* USART3_CTS_NSS */ > + bias-disable; > + }; > + }; > + > usbotg_hs_pins_a: usbotg-hs-0 { > pins { > pinmux = ; /* OTG_ID */