From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.4 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9173AC388F2 for ; Mon, 2 Nov 2020 16:04:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E2122225E for ; Mon, 2 Nov 2020 16:04:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="nzqwEq4v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726885AbgKBQEs (ORCPT ); Mon, 2 Nov 2020 11:04:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726792AbgKBQEp (ORCPT ); Mon, 2 Nov 2020 11:04:45 -0500 Received: from mail-wr1-x449.google.com (mail-wr1-x449.google.com [IPv6:2a00:1450:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D02CEC0617A6 for ; Mon, 2 Nov 2020 08:04:44 -0800 (PST) Received: by mail-wr1-x449.google.com with SMTP id t14so6652958wrs.2 for ; Mon, 02 Nov 2020 08:04:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=LscJFjoJLVax370bbjjUkdBy9lfnLd5L4hR3aqcqMxs=; b=nzqwEq4vTT8NHX0FUtAmfwZIPpfNr+OUJMFzbti3OSrPs3NVjotzFBReNwTxYV6AMz HWgsOD2MpXBezJQXeaZw0TT7LWf3COshRTz2OUPwuDdwhfuUwnootXaOFUZ3C+GhC6cT J/q3KcCZWJahgOQAhs7OaEzaCrii4O+J1VWsZ2ZQD6JWbOc/QvwviNgeONWUVt2VFIz1 MTF7ac62CjoqIN8eI1hsQhKJkjS0B2HVumQOYzgTBMBHFgiOGUaaxD5MFX7KESHyZH3M fw3ivDHY2fFTfYVyqmOI/ypD3eT5UzJNjMO8K5qQJeL6EO0h2KSJeL/6uzbCfakWuLVH imFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=LscJFjoJLVax370bbjjUkdBy9lfnLd5L4hR3aqcqMxs=; b=eSFhTEN44rsm9tbqnRxfJgpS3tMJwZXdlSCzBpcw/q8MlEBkoznEGzvqN9bvOI7gdE EkN8k2rR3vXqgO2Vi/jDZSpEnlkkTMooO/jwUbuRM3jP/tMMsfcLf7OkiH90KAbFDqJG Ha9Sty4zliHXZaa/aWGMNgg0A0RISAhjmWE1G6MrOvZJlpVVvznIIzP5sWHBptpgf5B/ WR11tH7sbzq4JCKDXHPcjcuUy84ALbp20wkeXdDqk3wULpHrycw/jIu77EdCoi4wEi9B 2kG/mnRZonphanOdH1sgoZGjZ2115VFxxjQJaP8nf4z4fB8+z9KS+6KpWD4K0CSoG+a2 opLg== X-Gm-Message-State: AOAM5315E788rZkaEmysC65ycrD+E2YnrglpCrj7vecy15ZL0TZayiiT Q5hVR1rYU8vanpIwqr5x4NGrs4eXbseZca/v X-Google-Smtp-Source: ABdhPJwzgPTE7ULrW+99l185z6FAhKICh/xtuRH7sRk/qJVb4hSzj455QPw9m3FHqWfqtOU6n1JLrXcnSLJT+Smj Sender: "andreyknvl via sendgmr" X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:a1c:e345:: with SMTP id a66mr16954306wmh.188.1604333083509; Mon, 02 Nov 2020 08:04:43 -0800 (PST) Date: Mon, 2 Nov 2020 17:03:47 +0100 In-Reply-To: Message-Id: Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v7 07/41] arm64: mte: Convert gcr_user into an exclude mask From: Andrey Konovalov To: Catalin Marinas , Will Deacon Cc: Vincenzo Frascino , kasan-dev@googlegroups.com, Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrey Konovalov Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vincenzo Frascino The gcr_user mask is a per thread mask that represents the tags that are excluded from random generation when the Memory Tagging Extension is present and an 'irg' instruction is invoked. gcr_user affects the behavior on EL0 only. Currently that mask is an include mask and it is controlled by the user via prctl() while GCR_EL1 accepts an exclude mask. Convert the include mask into an exclude one to make it easier the register setting. Note: This change will affect gcr_kernel (for EL1) introduced with a future patch. Signed-off-by: Vincenzo Frascino Signed-off-by: Andrey Konovalov Reviewed-by: Catalin Marinas --- Change-Id: Id15c0b47582fb51594bb26fb8353d78c7d0953c1 --- arch/arm64/include/asm/processor.h | 2 +- arch/arm64/kernel/mte.c | 29 +++++++++++++++-------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index fce8cbecd6bc..e8cfc41a92d4 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -154,7 +154,7 @@ struct thread_struct { #endif #ifdef CONFIG_ARM64_MTE u64 sctlr_tcf0; - u64 gcr_user_incl; + u64 gcr_user_excl; #endif }; diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 06ba6c923ab7..a9f03be75cef 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -141,23 +141,22 @@ static void set_sctlr_el1_tcf0(u64 tcf0) preempt_enable(); } -static void update_gcr_el1_excl(u64 incl) +static void update_gcr_el1_excl(u64 excl) { - u64 excl = ~incl & SYS_GCR_EL1_EXCL_MASK; /* - * Note that 'incl' is an include mask (controlled by the user via - * prctl()) while GCR_EL1 accepts an exclude mask. + * Note that the mask controlled by the user via prctl() is an + * include while GCR_EL1 accepts an exclude mask. * No need for ISB since this only affects EL0 currently, implicit * with ERET. */ sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); } -static void set_gcr_el1_excl(u64 incl) +static void set_gcr_el1_excl(u64 excl) { - current->thread.gcr_user_incl = incl; - update_gcr_el1_excl(incl); + current->thread.gcr_user_excl = excl; + update_gcr_el1_excl(excl); } void flush_mte_state(void) @@ -172,7 +171,7 @@ void flush_mte_state(void) /* disable tag checking */ set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE); /* reset tag generation mask */ - set_gcr_el1_excl(0); + set_gcr_el1_excl(SYS_GCR_EL1_EXCL_MASK); } void mte_thread_switch(struct task_struct *next) @@ -183,7 +182,7 @@ void mte_thread_switch(struct task_struct *next) /* avoid expensive SCTLR_EL1 accesses if no change */ if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); - update_gcr_el1_excl(next->thread.gcr_user_incl); + update_gcr_el1_excl(next->thread.gcr_user_excl); } void mte_suspend_exit(void) @@ -191,13 +190,14 @@ void mte_suspend_exit(void) if (!system_supports_mte()) return; - update_gcr_el1_excl(current->thread.gcr_user_incl); + update_gcr_el1_excl(current->thread.gcr_user_excl); } long set_mte_ctrl(struct task_struct *task, unsigned long arg) { u64 tcf0; - u64 gcr_incl = (arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT; + u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & + SYS_GCR_EL1_EXCL_MASK; if (!system_supports_mte()) return 0; @@ -218,10 +218,10 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) if (task != current) { task->thread.sctlr_tcf0 = tcf0; - task->thread.gcr_user_incl = gcr_incl; + task->thread.gcr_user_excl = gcr_excl; } else { set_sctlr_el1_tcf0(tcf0); - set_gcr_el1_excl(gcr_incl); + set_gcr_el1_excl(gcr_excl); } return 0; @@ -230,11 +230,12 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) long get_mte_ctrl(struct task_struct *task) { unsigned long ret; + u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK; if (!system_supports_mte()) return 0; - ret = task->thread.gcr_user_incl << PR_MTE_TAG_SHIFT; + ret = incl << PR_MTE_TAG_SHIFT; switch (task->thread.sctlr_tcf0) { case SCTLR_EL1_TCF0_NONE: -- 2.29.1.341.ge80a0c044ae-goog