From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B01FCC433E2 for ; Fri, 4 Sep 2020 14:59:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E4682073B for ; Fri, 4 Sep 2020 14:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730826AbgIDO7j (ORCPT ); Fri, 4 Sep 2020 10:59:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730799AbgIDO7h (ORCPT ); Fri, 4 Sep 2020 10:59:37 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97A51C061246 for ; Fri, 4 Sep 2020 07:59:37 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=localhost) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1kEDBW-0003Rl-CT; Fri, 04 Sep 2020 16:59:26 +0200 Message-ID: Subject: Re: [PATCH 09/13] arm64: dts: imx8mp-evk: Align pin configuration group names with schema From: Lucas Stach To: Krzysztof Kozlowski , Rob Herring , David Airlie , Daniel Vetter , Russell King , Christian Gmeiner , Lee Jones , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Sam Ravnborg , Li Yang , Robert Chiras , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, etnaviv@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Date: Fri, 04 Sep 2020 16:59:46 +0200 In-Reply-To: <20200904145312.10960-10-krzk@kernel.org> References: <20200904145312.10960-1-krzk@kernel.org> <20200904145312.10960-10-krzk@kernel.org> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fr, 2020-09-04 at 16:53 +0200, Krzysztof Kozlowski wrote: > Device tree schema expects pin configuration groups to end with 'grp' > suffix, otherwise dtbs_check complain with a warning like: > > ... 'usdhc3grp-100mhz', 'usdhc3grp-200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' > > Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lucas Stach > --- > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > index 3d535f1b3440..ad66f1286d95 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > @@ -157,7 +157,7 @@ > >; > }; > > - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > fsl,pins = < > MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 > >; > @@ -182,7 +182,7 @@ > >; > }; > > - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > fsl,pins = < > MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 > MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 > @@ -194,7 +194,7 @@ > >; > }; > > - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > fsl,pins = < > MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 > MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 > @@ -206,7 +206,7 @@ > >; > }; > > - pinctrl_usdhc2_gpio: usdhc2grp-gpio { > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > fsl,pins = < > MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 > >; > @@ -228,7 +228,7 @@ > >; > }; > > - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { > + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 > MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 > @@ -244,7 +244,7 @@ > >; > }; > > - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { > + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6