[PATCH 0/3] ARM: dts: wire up the power domains on Meson8/8b/8m2

[PATCH 0/3] ARM: dts: wire up the power domains on Meson8/8b/8m2

[Martin Blumenstingl]

Now that the meson-ee-pwrc driver has gained support for the power
domains on Meson8/Meson8b/Meson8m2 we can add it to the corresponding
.dtsi files.

So far this doesn't fix (or break) anything for me (probably because all
vendor u-boots are enabling the Ethernet power domains unconditionally).
But at least it's one preparation step which is needed for video output
in the future.


Martin Blumenstingl (3):
  ARM: dts: meson8: add power domain controller
  ARM: dts: meson8m2: add resets for the power domain controller
  ARM: dts: meson8b: add power domain controller

 arch/arm/boot/dts/meson8.dtsi   | 13 +++++++++++++
 arch/arm/boot/dts/meson8b.dtsi  | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/meson8m2.dtsi | 19 +++++++++++++++++++
 3 files changed, 59 insertions(+)

-- 
2.27.0

[PATCH 1/3] ARM: dts: meson8: add power domain controller

[Martin Blumenstingl]

The Meson8 SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index a4ab8b96d0eb..3d0ab2ac5332 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/meson8-ddr-clkc.h>
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
+#include <dt-bindings/power/meson8-power.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include "meson.dtsi"
@@ -452,6 +453,8 @@ temperature_calib: calib@1f4 {
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
+
+	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
 };
 
 &gpio_intc {
@@ -467,6 +470,16 @@ clkc: clock-controller {
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
+
+	pwrc: power-controller {
+		compatible = "amlogic,meson8-pwrc";
+		#power-domain-cells = <1>;
+		amlogic,ao-sysctrl = <&pmu>;
+		clocks = <&clkc CLKID_VPU>;
+		clock-names = "vpu";
+		assigned-clocks = <&clkc CLKID_VPU>;
+		assigned-clock-rates = <364285714>;
+	};
 };
 
 &hwrng {
-- 
2.27.0

[PATCH 2/3] ARM: dts: meson8m2: add resets for the power domain controller

[Martin Blumenstingl]

The Meson8m2 SoCs has introduced additional reset lines for the VPU
compared to Meson8. Also it uses a slightly different VPU clock
frequency compared to Meson8 since it can now achieve 364MHz thanks to
the addition of the GP_PLL.
Add the reset lines, VPU clock configuration and update the compatible
string so the implementation differences can be managed.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8m2.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi
index 2397ba06d608..c7ddbb210366 100644
--- a/arch/arm/boot/dts/meson8m2.dtsi
+++ b/arch/arm/boot/dts/meson8m2.dtsi
@@ -61,6 +61,25 @@ mux {
 	};
 };
 
+&pwrc {
+	compatible = "amlogic,meson8m2-pwrc";
+	resets = <&reset RESET_DBLK>,
+		 <&reset RESET_PIC_DC>,
+		 <&reset RESET_HDMI_APB>,
+		 <&reset RESET_HDMI_SYSTEM_RESET>,
+		 <&reset RESET_VENCI>,
+		 <&reset RESET_VENCP>,
+		 <&reset RESET_VDAC_4>,
+		 <&reset RESET_VENCL>,
+		 <&reset RESET_VIU>,
+		 <&reset RESET_VENC>,
+		 <&reset RESET_RDMA>;
+	reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
+		      "vencp", "vdac", "vencl", "viu", "venc", "rdma";
+	assigned-clocks = <&clkc CLKID_VPU>;
+	assigned-clock-rates = <364000000>;
+};
+
 &saradc {
 	compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
 };
-- 
2.27.0

[PATCH 3/3] ARM: dts: meson8b: add power domain controller

[Martin Blumenstingl]

The Meson8b SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index ba36168b9c1b..2069c57343e5 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/meson8-ddr-clkc.h>
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
+#include <dt-bindings/power/meson8-power.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
@@ -433,6 +434,8 @@ &ethmac {
 
 	resets = <&reset RESET_ETHERNET>;
 	reset-names = "stmmaceth";
+
+	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
 };
 
 &gpio_intc {
@@ -449,6 +452,30 @@ clkc: clock-controller {
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
+
+	pwrc: power-controller {
+		compatible = "amlogic,meson8b-pwrc";
+		#power-domain-cells = <1>;
+		amlogic,ao-sysctrl = <&pmu>;
+		resets = <&reset RESET_DBLK>,
+			 <&reset RESET_PIC_DC>,
+			 <&reset RESET_HDMI_APB>,
+			 <&reset RESET_HDMI_SYSTEM_RESET>,
+			 <&reset RESET_VENCI>,
+			 <&reset RESET_VENCP>,
+			 <&reset RESET_VDAC_4>,
+			 <&reset RESET_VENCL>,
+			 <&reset RESET_VIU>,
+			 <&reset RESET_VENC>,
+			 <&reset RESET_RDMA>;
+		reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
+			      "venci", "vencp", "vdac", "vencl", "viu",
+			      "venc", "rdma";
+		clocks = <&clkc CLKID_VPU>;
+		clock-names = "vpu";
+		assigned-clocks = <&clkc CLKID_VPU>;
+		assigned-clock-rates = <182142857>;
+	};
 };
 
 &hwrng {
-- 
2.27.0

Re: [PATCH 0/3] ARM: dts: wire up the power domains on Meson8/8b/8m2

[Neil Armstrong]

On 20/06/2020 18:10, Martin Blumenstingl wrote:
> Now that the meson-ee-pwrc driver has gained support for the power
> domains on Meson8/Meson8b/Meson8m2 we can add it to the corresponding
> .dtsi files.
> 
> So far this doesn't fix (or break) anything for me (probably because all
> vendor u-boots are enabling the Ethernet power domains unconditionally).
> But at least it's one preparation step which is needed for video output
> in the future.
> 
> 
> Martin Blumenstingl (3):
>   ARM: dts: meson8: add power domain controller
>   ARM: dts: meson8m2: add resets for the power domain controller
>   ARM: dts: meson8b: add power domain controller
> 
>  arch/arm/boot/dts/meson8.dtsi   | 13 +++++++++++++
>  arch/arm/boot/dts/meson8b.dtsi  | 27 +++++++++++++++++++++++++++
>  arch/arm/boot/dts/meson8m2.dtsi | 19 +++++++++++++++++++
>  3 files changed, 59 insertions(+)
> 

For the serie:
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH 0/3] ARM: dts: wire up the power domains on Meson8/8b/8m2

[Kevin Hilman]

On Sat, 20 Jun 2020 18:10:07 +0200, Martin Blumenstingl wrote:
> Now that the meson-ee-pwrc driver has gained support for the power
> domains on Meson8/Meson8b/Meson8m2 we can add it to the corresponding
> .dtsi files.
> 
> So far this doesn't fix (or break) anything for me (probably because all
> vendor u-boots are enabling the Ethernet power domains unconditionally).
> But at least it's one preparation step which is needed for video output
> in the future.
> 
> [...]

Applied, thanks!

[1/3] ARM: dts: meson8: add power domain controller
      commit: aecc72b14d11327804f7ca1fc76ca88a22cc1136
[2/3] ARM: dts: meson8m2: add resets for the power domain controller
      commit: c5d3d3cf00d5ed74359e71f7b5d003cf34ba014c
[3/3] ARM: dts: meson8b: add power domain controller
      commit: 9960cacbaeb1ccc1b2d9840cadb18844d48a337b

Best regards,
-- 
Kevin Hilman <khilman@baylibre.com>