From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD889C43381 for ; Mon, 25 Mar 2019 15:49:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 773082087E for ; Mon, 25 Mar 2019 15:49:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729348AbfCYPtd (ORCPT ); Mon, 25 Mar 2019 11:49:33 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:56660 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728563AbfCYPtc (ORCPT ); Mon, 25 Mar 2019 11:49:32 -0400 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2PFctTF093703 for ; Mon, 25 Mar 2019 11:49:30 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rf1dxsxc2-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 25 Mar 2019 11:49:29 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 25 Mar 2019 15:49:23 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2PFnMuR28377146 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 25 Mar 2019 15:49:22 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1B8BCA405C; Mon, 25 Mar 2019 15:49:22 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9BCC8A405F; Mon, 25 Mar 2019 15:49:21 +0000 (GMT) Received: from [9.145.37.149] (unknown [9.145.37.149]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 25 Mar 2019 15:49:21 +0000 (GMT) Subject: Re: [PATCH v3 7/7] ocxl: Provide global MMIO accessors for external drivers To: "Alastair D'Silva" , alastair@d-silva.org Cc: Greg Kurz , Andrew Donnellan , Arnd Bergmann , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org References: <20190320053448.2098-1-alastair@au1.ibm.com> <20190325054438.15022-1-alastair@au1.ibm.com> <20190325054438.15022-8-alastair@au1.ibm.com> From: Frederic Barrat Date: Mon, 25 Mar 2019 16:49:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <20190325054438.15022-8-alastair@au1.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 x-cbid: 19032515-0016-0000-0000-00000266EF0D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032515-0017-0000-0000-000032C21FC3 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-25_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903250116 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 25/03/2019 à 06:44, Alastair D'Silva a écrit : > From: Alastair D'Silva > > External drivers that communicate via OpenCAPI will need to make > MMIO calls to interact with the devices. > > Signed-off-by: Alastair D'Silva > Reviewed-by: Greg Kurz > --- Acked-by: Frederic Barrat > drivers/misc/ocxl/Makefile | 2 +- > drivers/misc/ocxl/mmio.c | 234 +++++++++++++++++++++++++++++++++++++ > include/misc/ocxl.h | 110 +++++++++++++++++ > 3 files changed, 345 insertions(+), 1 deletion(-) > create mode 100644 drivers/misc/ocxl/mmio.c > > diff --git a/drivers/misc/ocxl/Makefile b/drivers/misc/ocxl/Makefile > index bc4e39bfda7b..d07d1bb8e8d4 100644 > --- a/drivers/misc/ocxl/Makefile > +++ b/drivers/misc/ocxl/Makefile > @@ -1,7 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0+ > ccflags-$(CONFIG_PPC_WERROR) += -Werror > > -ocxl-y += main.o pci.o config.o file.o pasid.o > +ocxl-y += main.o pci.o config.o file.o pasid.o mmio.o > ocxl-y += link.o context.o afu_irq.o sysfs.o trace.o > ocxl-y += core.o > obj-$(CONFIG_OCXL) += ocxl.o > diff --git a/drivers/misc/ocxl/mmio.c b/drivers/misc/ocxl/mmio.c > new file mode 100644 > index 000000000000..aae713db4ebe > --- /dev/null > +++ b/drivers/misc/ocxl/mmio.c > @@ -0,0 +1,234 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +// Copyright 2019 IBM Corp. > +#include > +#include "trace.h" > +#include "ocxl_internal.h" > + > +int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 *val) > +{ > + if (offset > afu->config.global_mmio_size - 4) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + *val = readl_be((char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + *val = readl((char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_read32); > + > +int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 *val) > +{ > + if (offset > afu->config.global_mmio_size - 8) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + *val = readq_be((char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + *val = readq((char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_read64); > + > +int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 val) > +{ > + if (offset > afu->config.global_mmio_size - 4) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + writel_be(val, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + writel(val, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_write32); > + > +int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 val) > +{ > + if (offset > afu->config.global_mmio_size - 8) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + writeq_be(val, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + writeq(val, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_write64); > + > +int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 mask) > +{ > + u32 tmp; > + > + if (offset > afu->config.global_mmio_size - 4) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + tmp = readl_be((char *)afu->global_mmio_ptr + offset); > + tmp |= mask; > + writel_be(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + tmp = readl((char *)afu->global_mmio_ptr + offset); > + tmp |= mask; > + writel(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_set32); > + > +int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 mask) > +{ > + u64 tmp; > + > + if (offset > afu->config.global_mmio_size - 8) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + tmp = readq_be((char *)afu->global_mmio_ptr + offset); > + tmp |= mask; > + writeq_be(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + tmp = readq((char *)afu->global_mmio_ptr + offset); > + tmp |= mask; > + writeq(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_set64); > + > +int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 mask) > +{ > + u32 tmp; > + > + if (offset > afu->config.global_mmio_size - 4) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + tmp = readl_be((char *)afu->global_mmio_ptr + offset); > + tmp &= ~mask; > + writel_be(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + tmp = readl((char *)afu->global_mmio_ptr + offset); > + tmp &= ~mask; > + writel(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_clear32); > + > +int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 mask) > +{ > + u64 tmp; > + > + if (offset > afu->config.global_mmio_size - 8) > + return -EINVAL; > + > +#ifdef __BIG_ENDIAN__ > + if (endian == OCXL_HOST_ENDIAN) > + endian = OCXL_BIG_ENDIAN; > +#endif > + > + switch (endian) { > + case OCXL_BIG_ENDIAN: > + tmp = readq_be((char *)afu->global_mmio_ptr + offset); > + tmp &= ~mask; > + writeq_be(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + > + default: > + tmp = readq((char *)afu->global_mmio_ptr + offset); > + tmp &= ~mask; > + writeq(tmp, (char *)afu->global_mmio_ptr + offset); > + break; > + } > + > + writeq(tmp, (char *)afu->global_mmio_ptr + offset); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(ocxl_global_mmio_clear64); > diff --git a/include/misc/ocxl.h b/include/misc/ocxl.h > index 1b48e9d63abb..e0742c00fb72 100644 > --- a/include/misc/ocxl.h > +++ b/include/misc/ocxl.h > @@ -45,6 +45,12 @@ struct ocxl_fn_config { > s8 max_afu_index; > }; > > +enum ocxl_endian { > + OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */ > + OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */ > + OCXL_HOST_ENDIAN = 2, /**< AFU data is the same endianness as the host */ > +}; > + > // These are opaque outside the ocxl driver > struct ocxl_afu; > struct ocxl_fn; > @@ -236,6 +242,110 @@ void ocxl_afu_set_private(struct ocxl_afu *afu, void *private); > */ > void *ocxl_afu_get_private(struct ocxl_afu *dev); > > +// Global MMIO > +/** > + * Read a 32 bit value from global MMIO > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @val: returns the value > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 *val); > + > +/** > + * Read a 64 bit value from global MMIO > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @val: returns the value > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 *val); > + > +/** > + * Write a 32 bit value to global MMIO > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @val: The value to write > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 val); > + > +/** > + * Write a 64 bit value to global MMIO > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @val: The value to write > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 val); > + > +/** > + * Set bits in a 32 bit global MMIO register > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @mask: a mask of the bits to set > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 mask); > + > +/** > + * Set bits in a 64 bit global MMIO register > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @mask: a mask of the bits to set > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 mask); > + > +/** > + * Set bits in a 32 bit global MMIO register > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @mask: a mask of the bits to set > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u32 mask); > + > +/** > + * Set bits in a 64 bit global MMIO register > + * > + * @afu: The AFU > + * @offset: The Offset from the start of MMIO > + * @endian: the endianness that the MMIO data is in > + * @mask: a mask of the bits to set > + * > + * Returns 0 for success, negative on error > + */ > +int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset, > + enum ocxl_endian endian, u64 mask); > > // Functions left here are for compatibility with the cxlflash driver > >