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From: Marc Zyngier <marc.zyngier@arm.com>
To: Christoph Hellwig <hch@lst.de>, Rob Herring <robh+dt@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	atish.patra@wdc.com, Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	linux-riscv@lists.infradead.org,
	Stafford Horne <shorne@gmail.com>
Subject: Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Wed, 8 Aug 2018 17:47:40 +0100	[thread overview]
Message-ID: <bb671fe1-6c43-3218-0096-7c5280ffb6b5@arm.com> (raw)
In-Reply-To: <20180808150938.GA32274@lst.de>

On 08/08/18 16:09, Christoph Hellwig wrote:
> On Wed, Aug 08, 2018 at 08:16:14AM -0600, Rob Herring wrote:
>> Is 1.0 an actual version number corresponding to an exact, revision
>> controlled version of the IP or just something you made up? Looks like
>> the latter to me and I'm not a fan of s/w folks making up version
>> numbers for h/w. Standard naming convention is <vendor>,<soc>-<block>
>> unless you have good reason to deviate (IP for FPGAs where version
>> numbers are exposed to customers is one example).
>>
>> And defining a version 2 when you find a quirk doesn't work. You've
>> already shipped the DT. You need to be able to fix issues with just an
>> OS update. This is why you are supposed to define a compatible string
>> for each and every SoC (and use a fallback when they are "the
>> same"TM).
> 
> Can you point to some existing examples of the multiple offered
> compatible strings and what is actually matched for something that
> largely hasn't changed?
> 
> For example the documentation for the arm GICv3 binding seems to just
> match for arm,gic-v3.  On the other hand the GIC driver seems to match
> for a lot of different strings.

The original GIC driver deals with 2.5 revisions of the architecture
(yes, there was something pre-GICv1...), and implementers have been
creative to the extreme. Still, we could have done without most of these
compat strings. Hindsight and all that jazz.

GICv3 is a much more controlled architecture, and although people have
come up with a number of turds masquerading as implementations, it has
never been bad enough to mandate a different set of compat strings.
Also, you cannot describe that kind of stuff in ACPI, and we need to
support both, so we've come up with different ways of handling this.

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2018-08-08 16:47 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig
2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig
2018-08-08 14:44   ` Rob Herring
2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig
2018-08-08 14:43   ` Rob Herring
2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 22:08   ` Atish Patra
2018-08-03 13:30     ` Christoph Hellwig
2018-08-06 20:59     ` Rob Herring
2018-08-07  7:20       ` Christoph Hellwig
2018-08-08  2:17       ` Palmer Dabbelt
2018-08-08  6:42         ` Atish Patra
2018-08-08 14:16         ` Rob Herring
2018-08-08 15:09           ` Christoph Hellwig
2018-08-08 16:47             ` Marc Zyngier [this message]
2018-08-08 16:57               ` Christoph Hellwig
2018-08-09 10:19                 ` Marc Zyngier
2018-08-08 19:38           ` Palmer Dabbelt
2018-08-08 23:32             ` Rob Herring
2018-08-09  6:29               ` Palmer Dabbelt
2018-08-09  6:43                 ` Christoph Hellwig
2018-08-10 16:57                 ` Rob Herring
2018-08-10 20:09                   ` Palmer Dabbelt
2018-08-13 14:09                     ` Rob Herring
2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-08-02 22:19   ` Atish Patra
2018-08-03 12:33     ` Christoph Hellwig
2018-08-04  9:58       ` Christoph Hellwig
2018-08-06 20:34       ` Palmer Dabbelt
2018-08-08  6:47         ` Atish Patra
2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-02 23:13   ` Atish Patra
2018-08-03 12:29     ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-02 23:21   ` Atish Patra
2018-08-03 12:31     ` Christoph Hellwig
2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt
2018-08-03  7:49   ` Thomas Gleixner

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