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[94.29.41.50]) by smtp.googlemail.com with ESMTPSA id z18sm2402757lja.55.2020.08.06.06.46.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Aug 2020 06:46:15 -0700 (PDT) Subject: Re: [Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver To: Rajesh Gumasta , ldewangan@nvidia.com, jonathanh@nvidia.com, vkoul@kernel.org, dan.j.williams@intel.com, thierry.reding@gmail.com, p.zabel@pengutronix.de, dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kyarlagadda@nvidia.com, Pavan Kunapuli References: <1596699006-9934-1-git-send-email-rgumasta@nvidia.com> <1596699006-9934-3-git-send-email-rgumasta@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Thu, 6 Aug 2020 16:46:14 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1596699006-9934-3-git-send-email-rgumasta@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 06.08.2020 10:30, Rajesh Gumasta пишет: ... > +/* > + * Save and restore csr and channel register on pm_suspend > + * and pm_resume respectively > + */ > +static int __maybe_unused tegra_dma_pm_suspend(struct device *dev) > +{ > + struct tegra_dma *tdma = dev_get_drvdata(dev); > + int i; > + > + for (i = 0; i < tdma->chip_data->nr_channels; i++) { > + struct tegra_dma_channel *tdc = &tdma->channels[i]; > + struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; > + > + ch_reg->csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); > + ch_reg->src_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR); > + ch_reg->dst_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR); > + ch_reg->high_addr_ptr = tdc_read(tdc, > + TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR); > + ch_reg->mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); > + ch_reg->mmio_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ); > + ch_reg->wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT); > + } > + return 0; > +} > + > +static int __maybe_unused tegra_dma_pm_resume(struct device *dev) > +{ > + struct tegra_dma *tdma = dev_get_drvdata(dev); > + int i; > + > + for (i = 0; i < tdma->chip_data->nr_channels; i++) { > + struct tegra_dma_channel *tdc = &tdma->channels[i]; > + struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; > + > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_reg->wcount); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_reg->dst_ptr); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_reg->src_ptr); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, > + ch_reg->high_addr_ptr); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_reg->mmio_seq); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_reg->mc_seq); > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, > + (ch_reg->csr & ~TEGRA_GPCDMA_CSR_ENB)); > + } > + return 0; > +} > + > +static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = { > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume) > +}; Please explain why this is needed. All DMA should be stopped (not paused) on system's suspend, shouldn't it?