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Fri, 8 Nov 2019 10:32:56 +0000 (UTC) Received: from [10.36.116.54] (ovpn-116-54.ams2.redhat.com [10.36.116.54]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4F2931A8D8; Fri, 8 Nov 2019 10:32:53 +0000 (UTC) From: Auger Eric Subject: Re: [PATCH v7 01/11] iommu/vt-d: Cache virtual command capability register To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse , Alex Williamson , Jean-Philippe Brucker Cc: Yi Liu , "Tian, Kevin" , Raj Ashok , Christoph Hellwig , Lu Baolu , Jonathan Cameron References: <1571946904-86776-1-git-send-email-jacob.jun.pan@linux.intel.com> <1571946904-86776-2-git-send-email-jacob.jun.pan@linux.intel.com> Message-ID: Date: Fri, 8 Nov 2019 11:32:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1571946904-86776-2-git-send-email-jacob.jun.pan@linux.intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: aPiaQ9JyNAWA4YQ0AdCh0w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacob, On 10/24/19 9:54 PM, Jacob Pan wrote: > Virtual command registers are used in the guest only, to prevent > vmexit cost, we cache the capability and store it during initialization. >=20 > Signed-off-by: Jacob Pan > --- > drivers/iommu/dmar.c | 1 + > include/linux/intel-iommu.h | 4 ++++ > 2 files changed, 5 insertions(+) >=20 > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > index eecd6a421667..49bb7d76e646 100644 > --- a/drivers/iommu/dmar.c > +++ b/drivers/iommu/dmar.c > @@ -950,6 +950,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 p= hys_addr) > =09=09warn_invalid_dmar(phys_addr, " returns all ones"); > =09=09goto unmap; > =09} > +=09iommu->vccap =3D dmar_readq(iommu->reg + DMAR_VCCAP_REG); > =20 > =09/* the registers might be more than one page */ > =09map_size =3D max_t(int, ecap_max_iotlb_offset(iommu->ecap), > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index ed11ef594378..2e1bed9b7eef 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -186,6 +186,9 @@ > #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) > #define ecap_sc_support(e)=09((e >> 7) & 0x1) /* Snooping Control */ > =20 > +/* Virtual command interface capabilities */ > +#define vccap_pasid(v)=09=09((v & DMA_VCS_PAS)) /* PASID allocation */ > + > /* IOTLB_REG */ > #define DMA_TLB_FLUSH_GRANU_OFFSET 60 > #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) > @@ -520,6 +523,7 @@ struct intel_iommu { > =09u64=09=09reg_size; /* size of hw register set */ > =09u64=09=09cap; > =09u64=09=09ecap; > +=09u64=09=09vccap; > =09u32=09=09gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ > =09raw_spinlock_t=09register_lock; /* protect register handling */ > =09int=09=09seq_id;=09/* sequence id of the iommu */ >=20 with DMA_VCS_PAS's move in this patch as pointed out by Kevin or vccap_pasid() move to patch 3, feel free to add Reviewed-by: Eric Auger Eric