From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69612C433E0 for ; Thu, 4 Mar 2021 20:59:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33F8564F23 for ; Thu, 4 Mar 2021 20:59:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236564AbhCDU7E (ORCPT ); Thu, 4 Mar 2021 15:59:04 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:33932 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230413AbhCDU6i (ORCPT ); Thu, 4 Mar 2021 15:58:38 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 124KvUS0069529; Thu, 4 Mar 2021 14:57:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614891450; bh=7EsRPtM7ZM2gT07lEoewcPHopX7Slw9tPNibNpx45xs=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Ocw9pZeLd2sdoKP4SRVD87N3USu/oAGAE1o03ksr3GrAY6WQQxFRRgO3T4v1dSfXf kpmQvlik1z6y+82D2Xccw8eLlKaQw1CSCEps2PkmwsKbK11BFRKk8reegslaZYur1k yvaIg7cUs3TM/X5afWzavWLss2zf400cc/FL1QqM= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 124KvUlv012323 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 4 Mar 2021 14:57:30 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 4 Mar 2021 14:57:29 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 4 Mar 2021 14:57:29 -0600 Received: from [10.250.100.73] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 124KvRVu058496; Thu, 4 Mar 2021 14:57:27 -0600 Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order To: Tony Lindgren , Daniel Lezcano , Thomas Gleixner CC: Keerthy , , , References: <20210304072135.52712-1-tony@atomide.com> <20210304072135.52712-2-tony@atomide.com> From: Grygorii Strashko Message-ID: Date: Thu, 4 Mar 2021 22:57:02 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210304072135.52712-2-tony@atomide.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/03/2021 09:21, Tony Lindgren wrote: > When the timer is configured in posted mode, we need to check the write- > posted status register (TWPS) before writing to the register. > > We now check TWPS after the write starting with commit 52762fbd1c47 > ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource > support"). > > For example, in the TRM for am571x the following is documented in chapter > "22.2.4.13.1.1 Write Posting Synchronization Mode": > > "For each register, a status bit is provided in the timer write-posted > status (TWPS) register. In this mode, it is mandatory that software check > this status bit before any write access. If a write is attempted to a > register with a previous access pending, the previous access is discarded > without notice." > > The regression happened when I updated the code to use standard read/write > accessors for the driver instead of using __omap_dm_timer_load_start(). > We have__omap_dm_timer_load_start() check the TWPS status correctly using > __omap_dm_timer_write(). > > Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support") > Signed-off-by: Tony Lindgren > --- > drivers/clocksource/timer-ti-dm-systimer.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksource/timer-ti-dm-systimer.c > --- a/drivers/clocksource/timer-ti-dm-systimer.c > +++ b/drivers/clocksource/timer-ti-dm-systimer.c > @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles, > struct dmtimer_systimer *t = &clkevt->t; > void __iomem *pend = t->base + t->pend; > > - writel_relaxed(0xffffffff - cycles, t->base + t->counter); > while (readl_relaxed(pend) & WP_TCRR) > cpu_relax(); > + writel_relaxed(0xffffffff - cycles, t->base + t->counter); > > - writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); > while (readl_relaxed(pend) & WP_TCLR) > cpu_relax(); > + writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); It seems static [and inline] helper here could be better solution. no? > > return 0; > } > @@ -490,18 +490,18 @@ static int dmtimer_set_periodic(struct clock_event_device *evt) > dmtimer_clockevent_shutdown(evt); > > /* Looks like we need to first set the load value separately */ > - writel_relaxed(clkevt->period, t->base + t->load); > while (readl_relaxed(pend) & WP_TLDR) > cpu_relax(); > + writel_relaxed(clkevt->period, t->base + t->load); > > - writel_relaxed(clkevt->period, t->base + t->counter); > while (readl_relaxed(pend) & WP_TCRR) > cpu_relax(); > + writel_relaxed(clkevt->period, t->base + t->counter); > > - writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, > - t->base + t->ctrl); > while (readl_relaxed(pend) & WP_TCLR) > cpu_relax(); > + writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, > + t->base + t->ctrl); > > return 0; > } > -- Best regards, grygorii