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From: Paolo Bonzini <bonzini@gnu.org>
To: "puwen@hygon.cn" <puwen@hygon.cn>, tglx <tglx@linutronix.de>,
	bp <bp@alien8.de>, "thomas.lendacky" <thomas.lendacky@amd.com>,
	mingo <mingo@redhat.com>, hpa <hpa@zytor.com>,
	peterz <peterz@infradead.org>, "tony.luck" <tony.luck@intel.com>,
	rkrcmar <rkrcmar@redhat.com>,
	"boris.ostrovsky" <boris.ostrovsky@oracle.com>,
	jgross <jgross@suse.com>, rjw <rjw@rjwysocki.net>,
	lenb <lenb@kernel.org>, "viresh.kumar" <viresh.kumar@linaro.org>,
	mchehab <mchehab@kernel.org>, trenn <trenn@suse.com>,
	shuah <shuah@kernel.org>, x86 <x86@kernel.org>
Cc: linux-kernel <linux-kernel@vger.kernel.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	kvm <kvm@vger.kernel.org>
Subject: Re: [PATCH v2 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system
Date: Sun, 29 Jul 2018 01:42:46 +0200	[thread overview]
Message-ID: <bd73d865-acb3-66e5-a37a-dc4859e5f002@gnu.org> (raw)
In-Reply-To: <201807290021145963620@hygon.cn>

On 28/07/2018 18:48, puwen@hygon.cn wrote:
> Hi Paolo,
> 
> Thanks for your feedback.
> 
> As we described in the patch description, current Hygon Family 18h share
> most architecture with AMD Family 17h. But Hygon Family 18h are not the
> same with AMD family 17h, as it removed some features such as SME/SEV in
> Dhyana.

If the maintainers are okay with X86_FEATURE_HYGON that's certainly
fine, however I think you can improve the consistency of the patches in
a few ways.

Lack of SME/SEV is not an issue, since there are AMD Zen chips without
SME/SEV too, but potential incompatibility with future AMD fam18h chips
is important.  Therefore, code like this one in amd_uncore_init


-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 		return -ENODEV;

 	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 		return -ENODEV;

-	if (boot_cpu_data.x86 == 0x17) {
+	if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {

should check explicitly for Hygon before checking for family 18h.  The
same applies to the edac patch that I've just sent an answer to.

On the other hand, in many cases the AMD code is testing something like
"AMD && family >= 0x0f".  In this case you have a mix of:

- duplicate code for HYGON, such as modern_apic or mce_is_correctable

- change the condition to (AMD || HYGON) && family >= 0x0f, such as
k8_check_syscfg_dram_mod_en and amd_special_default_mtrr

- change the condition to (AMD && family >= 0x0f) || (HYGON && family >=
0x18), such as smp_quirk_init_udelay

I couldn't find any case where you used (AMD && family >= 0x0f) ||
HYGON, but I think it would be clearer in most cases than all the above
three alternatives.

In general, I would duplicate code if and only if the AMD code is a maze
of if/elseif/elseif.  In particular, code like this

	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTL)
 			return (msr - MSR_F15H_PERF_CTL) >> 1;
 		return msr - MSR_K7_EVNTSEL0;
+	case X86_VENDOR_HYGON:
+		if (msr >= MSR_F15H_PERF_CTL)
+			return (msr - MSR_F15H_PERF_CTL) >> 1;
+		return msr - MSR_K7_EVNTSEL0;

or this

	case X86_VENDOR_AMD:
 		rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
 		msr = lo | ((u64)hi << 32);
 		return !(msr & MSR_K7_HWCR_CPB_DIS);
+	case X86_VENDOR_HYGON:
+		rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
+		msr = lo | ((u64)hi << 32);
+		return !(msr & MSR_K7_HWCR_CPB_DIS);

looks a bit silly, and you already have several cases when you are not
introducing duplication (e.g. __mcheck_cpu_init_early).  On the other
hand, code like xen_pmu_arch_init can be very simple for Hygon and so it
may be useful to have a separate branch.

Thanks,

Paolo

  parent reply	other threads:[~2018-07-28 23:42 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-23 13:20 [PATCH v2 00/17] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-07-23 13:20 ` [PATCH v2 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen
2018-07-24 18:14   ` Paolo Bonzini
     [not found]     ` <201807290021145963620@hygon.cn>
2018-07-28 23:42       ` Paolo Bonzini [this message]
2018-07-30 16:42         ` Pu Wen
2018-07-23 13:20 ` [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Pu Wen
2018-07-23 13:20 ` [PATCH v2 03/17] x86/mtrr: get MTRR number and support TOP_MEM2 Pu Wen
2018-07-23 13:20 ` [PATCH v2 04/17] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen
2018-07-23 13:20 ` [PATCH v2 05/17] x86/perfctr: return perf counter and event selection bit offset Pu Wen
2018-07-23 13:20 ` [PATCH v2 06/17] x86/nops: init ideal_nops for Hygon Pu Wen
2018-07-23 13:20 ` [PATCH v2 07/17] x86/pci: add Hygon PCI vendor and northbridge support Pu Wen
2018-07-23 13:20 ` [PATCH v2 08/17] x86/apic: add modern APIC support for Hygon Pu Wen
2018-07-23 13:20 ` [PATCH v2 09/17] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen
2018-07-23 13:20 ` [PATCH v2 10/17] x86/events: enable Hygon support to PMU infrastructure Pu Wen
2018-07-23 13:20 ` [PATCH v2 11/17] x86/mce: enable Hygon support to MCE infrastructure Pu Wen
2018-07-23 13:20 ` [PATCH v2 12/17] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen
2018-07-23 13:20 ` [PATCH v2 13/17] x86/xen: enable Hygon support to Xen Pu Wen
2018-07-23 13:20 ` [PATCH v2 14/17] driver/acpi: enable Hygon support to ACPI driver Pu Wen
2018-07-23 13:20 ` [PATCH v2 15/17] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen
2018-07-23 13:20 ` [PATCH v2 16/17] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen
2018-07-28 23:42   ` Paolo Bonzini
2018-07-30 16:43     ` Pu Wen
2018-07-31  7:38       ` Paolo Bonzini
2018-07-31 10:46         ` Pu Wen

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