From: Dave Hansen <dave.hansen@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
linux-kernel@vger.kernel.org, x86@kernel.org,
linux-pm@vger.kernel.org
Cc: tglx@linutronix.de, dave.hansen@linux.intel.com,
peterz@infradead.org, bp@alien8.de, rafael@kernel.org,
ravi.v.shankar@intel.com
Subject: Re: [PATCH v2 1/2] x86/fpu: Add a helper to prepare AMX state for low-power CPU idle
Date: Wed, 9 Mar 2022 14:46:30 -0800 [thread overview]
Message-ID: <bde83c5f-ffe9-d548-de08-de3e14738bf0@intel.com> (raw)
In-Reply-To: <20220309223431.26560-2-chang.seok.bae@intel.com>
On 3/9/22 14:34, Chang S. Bae wrote:
> +/*
> + * Initialize register state that may prevent from entering low-power idle.
> + * This function will be invoked from the cpuidle driver only when needed.
> + */
> +void fpu_idle_fpregs(void)
> +{
> + if (!fpu_state_size_dynamic())
> + return;
Is this check just an optimization? I'm having trouble imagining a
situation where we would have:
(xfeatures_in_use() & XFEATURE_MASK_XTILE) == true
but
fpu_state_size_dynamic() == false
> + if (xfeatures_in_use() & XFEATURE_MASK_XTILE) {
> + tile_release();
> + fpregs_deactivate(¤t->thread.fpu);
> + }
> +}
xfeatures_in_use() isn't exactly expensive either.
next prev parent reply other threads:[~2022-03-09 22:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 22:34 [PATCH v2 0/2] x86/fpu: Make AMX state ready for CPU idle Chang S. Bae
2022-03-09 22:34 ` [PATCH v2 1/2] x86/fpu: Add a helper to prepare AMX state for low-power " Chang S. Bae
2022-03-09 22:46 ` Dave Hansen [this message]
2022-03-09 23:12 ` Chang S. Bae
2022-03-10 0:24 ` Dave Hansen
2022-03-10 21:00 ` Chang S. Bae
2022-03-22 7:05 ` Chang S. Bae
2022-03-09 22:34 ` [PATCH v2 2/2] intel_idle: Add a new flag to initialize the AMX state Chang S. Bae
2022-03-10 18:34 ` Rafael J. Wysocki
2022-03-10 18:50 ` Chang S. Bae
2022-03-11 7:33 ` Artem Bityutskiy
2022-03-22 7:06 ` Chang S. Bae
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