From: Sylwester Nawrocki <snawrocki@kernel.org>
To: Sam Protsenko <semen.protsenko@linaro.org>
Cc: "Ryu Euiyoul" <ryu.real@samsung.com>,
"Tom Gall" <tom.gall@linaro.org>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"John Stultz" <john.stultz@linaro.org>,
"Amit Pundir" <amit.pundir@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-samsung-soc@vger.kernel.org,
"Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com>,
"Sylwester Nawrocki" <s.nawrocki@samsung.com>,
"Paweł Chmiel" <pawel.mikolaj.chmiel@gmail.com>,
"Chanwoo Choi" <cw00.choi@samsung.com>,
"Tomasz Figa" <tomasz.figa@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>
Subject: Re: [PATCH v3 2/5] clk: samsung: clk-pll: Implement pll0831x PLL type
Date: Sat, 9 Oct 2021 22:25:39 +0200 [thread overview]
Message-ID: <bf48d35c-1b45-a111-5509-d81f92dd15e9@kernel.org> (raw)
In-Reply-To: <20211008154352.19519-3-semen.protsenko@linaro.org>
On 08.10.2021 17:43, Sam Protsenko wrote:
> pll0831x PLL is used in Exynos850 SoC for top-level fractional PLLs. The
> code was derived from very similar pll36xx type, with next differences:
>
> 1. Lock time for pll0831x is 500*P_DIV, when for pll36xx it's 3000*P_DIV
> 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require
> performing PLL lock procedure (which is done in pll36xx
> implementation)
> 3. The offset from PMS-values register to K-value register is 0x8 for
> pll0831x, when for pll36xx it's 0x4
>
> When defining pll0831x type, CON3 register offset should be provided as
> a "con" parameter of PLL() macro, like this:
>
> PLL(pll_0831x, 0, "fout_mmc_pll", "oscclk",
> PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, pll0831x_26mhz_tbl),
>
> To define PLL rates table, one can use PLL_36XX_RATE() macro, e.g.:
>
> PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124)
>
> as it's completely appropriate for pl0831x type and there is no sense in
> duplicating that.
>
> If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be
> possible to set new rate, with next error showing in kernel log:
>
> Could not lock PLL fout_mmc_pll
>
> That can happen for example if bootloader clears that bit beforehand.
> PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was
> cleared, it's assumed it was done for a reason and it shouldn't be
> possible to change that PLL's rate at all.
>
> Signed-off-by: Sam Protsenko<semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski<krzysztof.kozlowski@canonical.com>
> Acked-by: Chanwoo Choi<cw00.choi@samsung.com>
Applied, thanks.
next prev parent reply other threads:[~2021-10-09 20:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 15:43 [PATCH v3 0/5] clk: samsung: Introduce Exynos850 SoC clock driver Sam Protsenko
2021-10-08 15:43 ` [PATCH v3 1/5] clk: samsung: clk-pll: Implement pll0822x PLL type Sam Protsenko
2021-10-09 20:24 ` Sylwester Nawrocki
2021-10-08 15:43 ` [PATCH v3 2/5] clk: samsung: clk-pll: Implement pll0831x " Sam Protsenko
2021-10-09 20:25 ` Sylwester Nawrocki [this message]
2021-10-08 15:43 ` [PATCH v3 3/5] dt-bindings: clock: Add bindings definitions for Exynos850 CMU Sam Protsenko
2021-10-09 20:28 ` Sylwester Nawrocki
2021-10-08 15:43 ` [PATCH v3 4/5] dt-bindings: clock: Document Exynos850 CMU bindings Sam Protsenko
2021-10-09 20:40 ` Sylwester Nawrocki
2021-10-11 10:13 ` Sam Protsenko
2021-10-11 10:42 ` Sylwester Nawrocki
2021-10-12 8:13 ` Sam Protsenko
2021-10-15 13:46 ` Sylwester Nawrocki
2021-10-08 15:43 ` [PATCH v3 5/5] clk: samsung: Introduce Exynos850 clock driver Sam Protsenko
2021-10-12 8:14 ` Sam Protsenko
2021-10-15 13:30 ` Sylwester Nawrocki
2021-10-15 14:35 ` Sam Protsenko
2021-10-15 1:17 ` Chanwoo Choi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bf48d35c-1b45-a111-5509-d81f92dd15e9@kernel.org \
--to=snawrocki@kernel.org \
--cc=amit.pundir@linaro.org \
--cc=cw00.choi@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=john.stultz@linaro.org \
--cc=krzysztof.kozlowski@canonical.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=pawel.mikolaj.chmiel@gmail.com \
--cc=robh+dt@kernel.org \
--cc=ryu.real@samsung.com \
--cc=s.nawrocki@samsung.com \
--cc=sboyd@kernel.org \
--cc=semen.protsenko@linaro.org \
--cc=sumit.semwal@linaro.org \
--cc=tom.gall@linaro.org \
--cc=tomasz.figa@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).