From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD9F4C433F5 for ; Thu, 9 Sep 2021 04:46:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9013560F23 for ; Thu, 9 Sep 2021 04:46:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350485AbhIIEre (ORCPT ); Thu, 9 Sep 2021 00:47:34 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:27821 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349701AbhIIErb (ORCPT ); Thu, 9 Sep 2021 00:47:31 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1631162782; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=2aiD8EVkn8rCQHehlY7lNToGb+2zc8QVGnMllSyftjI=; b=EGx3Ph3zidI81WyCFHo9HtKss5hkvVM8KZd7dU/YCSy06IH78RvD6LzSNkckMSFHZQo7CXlJ 54JF3VVb1VLD5iS3lIQ4RJs/mlD1/YSr3VSVR7ASWbYHbb8V+QCfnC6oY9BHp25sl4A4/+Sg Tv6k6QSj6dfJHDCdrAHnLhPsZRs= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 6139918ce34848cb6aa98c85 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 09 Sep 2021 04:46:04 GMT Sender: rajpat=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id B0F32C4360D; Thu, 9 Sep 2021 04:46:04 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rajpat) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2171CC4338F; Thu, 9 Sep 2021 04:46:04 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 09 Sep 2021 10:16:04 +0530 From: rajpat@codeaurora.org To: Matthias Kaehlcke Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, skakit@codeaurora.org, sboyd@kernel.org, dianders@chromium.org Subject: Re: [PATCH V7 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes In-Reply-To: References: <1630643340-10373-1-git-send-email-rajpat@codeaurora.org> <1630643340-10373-4-git-send-email-rajpat@codeaurora.org> Message-ID: X-Sender: rajpat@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-09-03 22:03, Matthias Kaehlcke wrote: > On Fri, Sep 03, 2021 at 09:58:56AM +0530, Rajesh Patil wrote: >> From: Roja Rani Yarubandi >> >> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. >> >> Signed-off-by: Roja Rani Yarubandi >> Signed-off-by: Rajesh Patil >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 684 >> ++++++++++++++++++++++++++++++++++- >> 1 file changed, 682 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 7ec9871..5c6a1d7 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> ... >> >> + qup_spi0_data_clk: qup-spi0-data-clk { >> + pins = "gpio0", "gpio1", "gpio2"; >> + function = "qup00"; >> + }; >> + >> + qup_spi0_cs: qup-spi0-cs { >> + pins = "gpio3"; >> + function = "qup00"; >> + }; > > > I think we still want this for all SPI ports, which existed in previous > versions: > > qup_spi0_cs_gpio: qup-spi0-cs-gpio { > pins = "gpio3"; > function = "gpio"; > }; > > It just shouldn't be selected together with 'qup_spiN_cs'. > > Maybe a follow up patch would be good enough, so: > > Reviewed-by: Matthias Kaehlcke ok.shall we add qup_spiN_cs_gpio for all spi ports