From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A300AC433DB for ; Mon, 8 Feb 2021 12:05:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 656F664E9C for ; Mon, 8 Feb 2021 12:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233158AbhBHMF3 (ORCPT ); Mon, 8 Feb 2021 07:05:29 -0500 Received: from mga17.intel.com ([192.55.52.151]:46348 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232126AbhBHLnm (ORCPT ); Mon, 8 Feb 2021 06:43:42 -0500 IronPort-SDR: n6/wmL5Oe0KdgQIp3tIZ6C7xk0Pv+hMO+BcZ6TZV1rKjn88Hj+KXuIl3piIuv/0IOABq95lxUL 2SZ06NL++V8A== X-IronPort-AV: E=McAfee;i="6000,8403,9888"; a="161448544" X-IronPort-AV: E=Sophos;i="5.81,161,1610438400"; d="scan'208";a="161448544" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 03:41:43 -0800 IronPort-SDR: hm2VhsVrfb6wUBli739/bQvu86h2o8qp+XumRxBax8AuuH9k0dVSKC5/bI/9799JLrzMDHBAHx 68YTYmlSsf/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,161,1610438400"; d="scan'208";a="487380374" Received: from mattu-haswell.fi.intel.com (HELO [10.237.72.170]) ([10.237.72.170]) by fmsmga001.fm.intel.com with ESMTP; 08 Feb 2021 03:41:40 -0800 Subject: Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 To: Chunfeng Yun , Mathias Nyman Cc: Rob Herring , Matthias Brugger , Greg Kroah-Hartman , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Ikjoon Jang , Nicolas Boichat References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> <20210203102642.7353-2-chunfeng.yun@mediatek.com> <1612664833.5147.30.camel@mhfsdcap03> From: Mathias Nyman Autocrypt: addr=mathias.nyman@linux.intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1612664833.5147.30.camel@mhfsdcap03> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7.2.2021 4.27, Chunfeng Yun wrote: > Hi Mathias, > > On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote: >> There are 4 USB controllers on MT8195, the controllers (IP1~IP3, >> exclude IP0) have a wrong default SOF/ITP interval which is >> calculated from the frame counter clock 24Mhz by default, but >> in fact, the frame counter clock is 48Mhz, so we should set >> the accurate interval according to 48Mhz for those controllers. >> Note: the first controller no need set it. >> >> Signed-off-by: Chunfeng Yun >> --- >> v2: fix typo of comaptible >> --- >> drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> >> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c >> index 8f321f39ab96..0a68c4ac8b48 100644 >> --- a/drivers/usb/host/xhci-mtk.c >> +++ b/drivers/usb/host/xhci-mtk.c >> @@ -68,11 +68,71 @@ >> #define SSC_IP_SLEEP_EN BIT(4) >> #define SSC_SPM_INT_EN BIT(1) >> > Can I Read/Write the following xHCI controller's registers in > xhci-mtk.c? > > Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a > glue driver used to initialize clocks/power and IPPC registers which > don't belong to xHCI controller. > These *_EOF registers look like they are Mediatek vendor specific registers and not part of public xHCI register-level spec. So I think accessing them from xhci-mtk.c makes sense. If those register offsets are hardcoded like this in the Mediatek spec then this is fine, but if those offsets are found from a vendor specific xHCI extended capability entry (see xhci spec section 7) then we should dig them out from there. >> +/* xHCI csr */ >> +#define LS_EOF 0x930 >> +#define LS_EOF_OFFSET 0x89 >> + >> +#define FS_EOF 0x934 >> +#define FS_EOF_OFFSET 0x2e >> + >> +#define SS_GEN1_EOF 0x93c >> +#define SS_GEN1_EOF_OFFSET 0x78 >> + >> +#define HFCNTR_CFG 0x944 >> +#define ITP_DELTA_CLK (0xa << 1) >> +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) >> +#define FRMCNT_LEV1_RANG (0x12b << 8) >> +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) >> + >> +#define SS_GEN2_EOF 0x990 >> +#define SS_GEN2_EOF_OFFSET 0x3c >> +#define EOF_OFFSET_MASK GENMASK(11, 0) >> + >> enum ssusb_uwk_vers { >> SSUSB_UWK_V1 = 1, >> SSUSB_UWK_V2, >> }; >> >> +/* >> + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval >> + * is calculated from the frame counter clock 24M, but in fact, the clock >> + * is 48M, so need change the interval. >> + */ >> +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) >> +{ >> + struct device *dev = mtk->dev; >> + struct usb_hcd *hcd = mtk->hcd; >> + u32 value; >> + >> + if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) >> + return; >> + >> + value = readl(hcd->regs + HFCNTR_CFG); >> + value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); >> + value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); >> + writel(value, hcd->regs + HFCNTR_CFG); >> + >> + value = readl(hcd->regs + LS_EOF); >> + value &= ~EOF_OFFSET_MASK; >> + value |= LS_EOF_OFFSET; >> + writel(value, hcd->regs + LS_EOF); >> + >> + value = readl(hcd->regs + FS_EOF); >> + value &= ~EOF_OFFSET_MASK; >> + value |= FS_EOF_OFFSET; >> + writel(value, hcd->regs + FS_EOF); >> + >> + value = readl(hcd->regs + SS_GEN1_EOF); >> + value &= ~EOF_OFFSET_MASK; >> + value |= SS_GEN1_EOF_OFFSET; >> + writel(value, hcd->regs + SS_GEN1_EOF); >> + >> + value = readl(hcd->regs + SS_GEN2_EOF); >> + value &= ~EOF_OFFSET_MASK; >> + value |= SS_GEN2_EOF_OFFSET; >> + writel(value, hcd->regs + SS_GEN2_EOF); Minor nit about names, Register offsets from MMIO start are named *_EOF while clock multipliers? are named *_EOF_OFFSET. This was a bit confusing Thanks -Mathias