From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75788C25B06 for ; Fri, 5 Aug 2022 09:39:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240573AbiHEJjQ (ORCPT ); Fri, 5 Aug 2022 05:39:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229767AbiHEJjP (ORCPT ); Fri, 5 Aug 2022 05:39:15 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F909785A9; Fri, 5 Aug 2022 02:39:11 -0700 (PDT) Received: from [10.18.29.47] (10.18.29.47) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.9; Fri, 5 Aug 2022 17:39:09 +0800 Message-ID: Date: Fri, 5 Aug 2022 17:39:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Content-Language: en-US To: Krzysztof Kozlowski , , , , , , Rob Herring , Neil Armstrong , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl References: <20220805085716.5635-1-yu.tu@amlogic.com> <20220805085716.5635-3-yu.tu@amlogic.com> <19654574-bdc0-9fa5-6465-fc88b20e20c5@linaro.org> From: Yu Tu In-Reply-To: <19654574-bdc0-9fa5-6465-fc88b20e20c5@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.47] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, Thank you for your reply. On 2022/8/5 17:16, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 05/08/2022 10:57, Yu Tu wrote: >> Added information about the S4 SOC PLL Clock controller in DT. >> >> Signed-off-by: Yu Tu >> --- >> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >> index ff213618a598..a816b1f7694b 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi >> @@ -92,6 +92,14 @@ apb4: apb4@fe000000 { >> #size-cells = <2>; >> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; >> >> + clkc_pll: pll-clock-controller@8000 { > > Node names should be generic - clock-controller. > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > I will change to clkc_pll: clock-controller@8000, in next version. > > Best regards, > Krzysztof > > .