From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDB75C04EB8 for ; Sat, 1 Dec 2018 01:01:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB49D20673 for ; Sat, 1 Dec 2018 01:01:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB49D20673 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=telegraphics.com.au Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727181AbeLAMMS (ORCPT ); Sat, 1 Dec 2018 07:12:18 -0500 Received: from kvm5.telegraphics.com.au ([98.124.60.144]:38142 "EHLO kvm5.telegraphics.com.au" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726788AbeLAMLb (ORCPT ); Sat, 1 Dec 2018 07:11:31 -0500 Received: by kvm5.telegraphics.com.au (Postfix, from userid 502) id 1EDA2281EE; Fri, 30 Nov 2018 20:00:15 -0500 (EST) To: Geert Uytterhoeven Cc: Andreas Schwab , Arnd Bergmann , Stephen N Chivers , Thomas Gleixner , Kars de Jong , Daniel Lezcano , Michael Schmitz , John Stultz , Linus Walleij , linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: References: From: Finn Thain Subject: [PATCH v4 07/14] m68k: bvme6000: Convert to clocksource API Date: Sat, 01 Dec 2018 11:53:10 +1100 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a platform clocksource by adapting the existing arch_gettimeoffset implementation. Signed-off-by: Finn Thain Acked-by: Linus Walleij --- Changed since v3: - Use clk_offset variable to track the offset when the irq check is skipped. Changed since v2: - Don't check for timer interrupt in bvme6000_read_clk() when the timer is about to be reloaded. Changed since v1: - Moved clk_total access to within the irq lock. --- arch/m68k/bvme6000/config.c | 57 ++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c index c8b99d5516d1..8ebaabc931cd 100644 --- a/arch/m68k/bvme6000/config.c +++ b/arch/m68k/bvme6000/config.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -147,6 +148,21 @@ irqreturn_t bvme6000_abort_int (int irq, void *dev_id) return IRQ_HANDLED; } +static u64 bvme6000_read_clk(struct clocksource *cs); + +static struct clocksource bvme6000_clk = { + .name = "rtc", + .rating = 250, + .read = bvme6000_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static u32 clk_total, clk_offset; + +#define RTC_TIMER_CLOCK_FREQ 8000000 +#define RTC_TIMER_CYCLES (RTC_TIMER_CLOCK_FREQ / HZ) +#define RTC_TIMER_COUNT ((RTC_TIMER_CYCLES / 2) - 1) static irqreturn_t bvme6000_timer_int (int irq, void *dev_id) { @@ -158,6 +174,8 @@ static irqreturn_t bvme6000_timer_int (int irq, void *dev_id) local_irq_save(flags); msr = rtc->msr & 0xc0; rtc->msr = msr | 0x20; /* Ack the interrupt */ + clk_total += RTC_TIMER_CYCLES; + clk_offset = 0; timer_routine(0, NULL); local_irq_restore(flags); @@ -180,13 +198,13 @@ void bvme6000_sched_init (irq_handler_t timer_routine) rtc->msr = 0; /* Ensure timer registers accessible */ - if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, 0, "timer", + if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, IRQF_TIMER, "timer", timer_routine)) panic ("Couldn't register timer int"); rtc->t1cr_omr = 0x04; /* Mode 2, ext clk */ - rtc->t1msb = 39999 >> 8; - rtc->t1lsb = 39999 & 0xff; + rtc->t1msb = RTC_TIMER_COUNT >> 8; + rtc->t1lsb = RTC_TIMER_COUNT & 0xff; rtc->irr_icr1 &= 0xef; /* Route timer 1 to INTR pin */ rtc->msr = 0x40; /* Access int.cntrl, etc */ rtc->pfr_icr0 = 0x80; /* Just timer 1 ints enabled */ @@ -198,14 +216,14 @@ void bvme6000_sched_init (irq_handler_t timer_routine) rtc->msr = msr; + clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ); + if (request_irq(BVME_IRQ_ABORT, bvme6000_abort_int, 0, "abort", bvme6000_abort_int)) panic ("Couldn't register abort int"); } -/* This is always executed with interrupts disabled. */ - /* * NOTE: Don't accept any readings within 5us of rollover, as * the T1INT bit may be a little slow getting set. There is also @@ -213,14 +231,18 @@ void bvme6000_sched_init (irq_handler_t timer_routine) * results... */ -u32 bvme6000_gettimeoffset(void) +static u64 bvme6000_read_clk(struct clocksource *cs) { + unsigned long flags; volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE; - unsigned char msr = rtc->msr & 0xc0; + unsigned char msr, msb; unsigned char t1int, t1op; u32 v = 800000, ov; + local_irq_save(flags); + + msr = rtc->msr & 0xc0; rtc->msr = 0; /* Ensure timer registers accessible */ do { @@ -228,22 +250,25 @@ u32 bvme6000_gettimeoffset(void) t1int = rtc->msr & 0x20; t1op = pit->pcdr & 0x04; rtc->t1cr_omr |= 0x40; /* Latch timer1 */ - v = rtc->t1msb << 8; /* Read timer1 */ - v |= rtc->t1lsb; /* Read timer1 */ + msb = rtc->t1msb; /* Read timer1 */ + v = (msb << 8) | rtc->t1lsb; /* Read timer1 */ } while (t1int != (rtc->msr & 0x20) || t1op != (pit->pcdr & 0x04) || abs(ov-v) > 80 || - v > 39960); + v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100)); - v = 39999 - v; + v = RTC_TIMER_COUNT - v; if (!t1op) /* If in second half cycle.. */ - v += 40000; - v /= 8; /* Convert ticks to microseconds */ - if (t1int) - v += 10000; /* Int pending, + 10ms */ + v += RTC_TIMER_CYCLES / 2; + if (msb > 0 && t1int) + clk_offset = RTC_TIMER_CYCLES; rtc->msr = msr; - return v * 1000; + v += clk_offset + clk_total; + + local_irq_restore(flags); + + return v; } /* -- 2.18.1