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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: "Kroening, Gary" <gary.kroening@hpe.com>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"Travis, Mike" <mike.travis@hpe.com>,
	"Banman, Andrew" <abanman@hpe.com>,
	"Sivanich, Dimitri" <dimitri.sivanich@hpe.com>,
	"Anderson, Russ" <russ.anderson@hpe.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches
Date: Tue, 13 Mar 2018 13:28:37 -0400	[thread overview]
Message-ID: <c3e09140-8a5b-0fdd-82cc-03700be3b5a0@linux.intel.com> (raw)
In-Reply-To: <CAHp75VebU5NYXRDpG4pzYrKDmNLE6prGbecacq3gCyDQBJd=cA@mail.gmail.com>



On 3/13/2018 1:22 PM, Andy Shevchenko wrote:
> On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan <kan.liang@linux.intel.com> wrote:
>> On 3/13/2018 12:00 PM, Andy Shevchenko wrote:
>>> On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko
>>> <andy.shevchenko@gmail.com> wrote:
>>>> On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan <kan.liang@linux.intel.com>
>>>> wrote:
> 
>>>>> +#define SKX_CAPID6             0x9c
> 
>>>>> +       pci_read_config_dword(dev, SKX_CAPID6, &val);
> 
>>> Moreover, this is too non-flexible. Can't you find a capability based
>>> on CAP ID  + offset?
>>>
>>
>> It looks it doesn't use capability.
> 
> See below. It would be sad if it's true. (Will need comment in that case)
> 
>> 16:1e.3 System peripheral: Intel Corporation Sky Lake-E PCU Registers (rev
>> 04)
>> 00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
>> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> Can you instead provide
> % lspci -nk -vvv -xx -s 16:1e.3
> ?

$ lspci -nk -vvv -xx -s 16:1e.3
16:1e.3 0880: 8086:2083 (rev 04)
         Subsystem: 8086:0000
         Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- 
ParErr- Stepping- SERR- FastB2B- DisINTx-
         Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

  reply	other threads:[~2018-03-13 17:28 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-07 20:33 [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches Kroening, Gary
2018-03-13  1:42 ` Liang, Kan
2018-03-13  5:06   ` Kroening, Gary
2018-03-13 12:28     ` Liang, Kan
2018-03-13  5:24   ` Kroening, Gary
2018-03-13 15:58   ` Andy Shevchenko
2018-03-13 16:00     ` Andy Shevchenko
2018-03-13 17:15       ` Liang, Kan
2018-03-13 17:22         ` Andy Shevchenko
2018-03-13 17:28           ` Liang, Kan [this message]
2018-03-13 17:31             ` Andy Shevchenko
2018-03-13 17:16     ` Liang, Kan
2018-03-13 17:42       ` Liang, Kan
2018-03-13 17:46         ` Andy Shevchenko
2018-03-13 17:49           ` Andy Shevchenko
2018-03-13 17:50             ` Andy Shevchenko

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