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From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Alastair D'Silva <alastair@au1.ibm.com>, alastair@d-silva.org
Cc: stable@vger.kernel.org,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	Michael Ellerman <mpe@ellerman.id.au>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Thomas Gleixner <tglx@linutronix.de>, Qian Cai <cai@lca.pw>,
	Nicholas Piggin <npiggin@gmail.com>,
	Allison Randal <allison@lohutok.net>,
	Andrew Morton <akpm@linux-foundation.org>,
	Mike Rapoport <rppt@linux.vnet.ibm.com>,
	Michal Hocko <mhocko@suse.com>,
	David Hildenbrand <david@redhat.com>,
	linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB
Date: Sat, 14 Sep 2019 09:46:47 +0200
Message-ID: <c4760639-68e8-6969-d0eb-97f12f814109@c-s.fr> (raw)
In-Reply-To: <20190903052407.16638-2-alastair@au1.ibm.com>



Le 03/09/2019 à 07:23, Alastair D'Silva a écrit :
> From: Alastair D'Silva <alastair@d-silva.org>
> 
> When calling flush_icache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
> 
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.

Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S ?

Christophe

> 
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> Cc: stable@vger.kernel.org
> ---
>   arch/powerpc/kernel/misc_64.S | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index b55a7b4cb543..9bc0aa9aeb65 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
>   	subf	r8,r6,r4		/* compute length */
>   	add	r8,r8,r5		/* ensure we get enough */
>   	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of cache block size */
> -	srw.	r8,r8,r9		/* compute line count */
> +	srd.	r8,r8,r9		/* compute line count */
>   	beqlr				/* nothing to do? */
>   	mtctr	r8
>   1:	dcbst	0,r6
> @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
>   	subf	r8,r6,r4		/* compute length */
>   	add	r8,r8,r5
>   	lwz	r9,ICACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of Icache block size */
> -	srw.	r8,r8,r9		/* compute line count */
> +	srd.	r8,r8,r9		/* compute line count */
>   	beqlr				/* nothing to do? */
>   	mtctr	r8
>   2:	icbi	0,r6
> 

  reply index

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-03  5:23 [PATCH v2 0/6] powerpc: convert cache asm to C Alastair D'Silva
2019-09-03  5:23 ` [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB Alastair D'Silva
2019-09-14  7:46   ` Christophe Leroy [this message]
2019-09-16  3:25     ` Alastair D'Silva
2019-09-03  5:23 ` [PATCH v2 2/6] powerpc: define helpers to get L1 icache sizes Alastair D'Silva
2019-09-03  5:23 ` [PATCH v2 3/6] powerpc: Convert flush_icache_range & friends to C Alastair D'Silva
2019-09-03  6:08   ` Christophe Leroy
2019-09-03 11:25     ` Michael Ellerman
2019-09-04  3:23     ` Alastair D'Silva
2019-09-04 13:35       ` Segher Boessenkool
2019-09-03 13:04   ` Segher Boessenkool
2019-09-03 14:28     ` Christophe Leroy
2019-09-03 16:04       ` Segher Boessenkool
2019-09-03 17:05         ` Christophe Leroy
2019-09-03 18:31           ` Segher Boessenkool
2019-09-03 20:11             ` Gabriel Paubert
2019-09-04  3:42               ` Alastair D'Silva
2019-09-04  3:36         ` Alastair D'Silva
2019-09-03  5:23 ` [PATCH v2 4/6] powerpc: Chunk calls to flush_dcache_range in arch_*_memory Alastair D'Silva
2019-09-03  6:19   ` Christophe Leroy
2019-09-03  6:25     ` Alastair D'Silva
2019-09-03  6:51       ` Christophe Leroy
2019-09-04  4:11         ` Alastair D'Silva
2019-09-03  5:23 ` [PATCH v2 5/6] powerpc: Remove 'extern' from func prototypes in cache headers Alastair D'Silva
2019-09-03  6:21   ` Christophe Leroy
2019-09-03  5:24 ` [PATCH v2 6/6] powerpc: Don't flush caches when adding memory Alastair D'Silva
2019-09-03  6:23   ` Christophe Leroy
2019-09-03  6:27     ` Alastair D'Silva

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