From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: devicetree@vger.kernel.org, Stephen Boyd <swboyd@chromium.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Rajendra Nayak <rnayak@codeaurora.org>,
Sibi Sankar <sibis@codeaurora.org>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC
Date: Thu, 25 Feb 2021 15:00:19 +0530 [thread overview]
Message-ID: <c4b7ae4dd009f563e6786f4a41f09efa38636fb6.1614244789.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1614244789.git.saiprakash.ranjan@codeaurora.org>
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3b86052b78bc..aeeb47c70c3a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -338,6 +338,13 @@ uart5: serial@994000 {
};
};
+ system-cache-controller@9200000 {
+ compatible = "qcom,sc7280-llcc";
+ reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0xb220000 0 0x30000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-02-25 9:33 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-25 9:30 [PATCH 0/9] qcom/sc7280: Enable various hardware blocks on SC7280 SoC Sai Prakash Ranjan
2021-02-25 9:30 ` [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280 Sai Prakash Ranjan
2021-02-25 19:35 ` Stephen Boyd
2021-03-06 20:47 ` Rob Herring
2021-02-25 9:30 ` [PATCH 2/9] soc: qcom: llcc: Add configuration data " Sai Prakash Ranjan
2021-02-25 9:30 ` Sai Prakash Ranjan [this message]
2021-02-25 19:37 ` [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC Stephen Boyd
2021-02-26 8:04 ` Sai Prakash Ranjan
2021-02-26 18:45 ` Stephen Boyd
2021-02-27 13:58 ` Sai Prakash Ranjan
2021-03-01 4:21 ` Stephen Boyd
2021-02-25 9:30 ` [PATCH 4/9] dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280 Sai Prakash Ranjan
2021-02-25 14:13 ` Manivannan Sadhasivam
2021-02-25 19:38 ` Stephen Boyd
2021-02-25 9:30 ` [PATCH 5/9] arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC Sai Prakash Ranjan
2021-02-25 14:12 ` Manivannan Sadhasivam
2021-02-25 19:38 ` Stephen Boyd
2021-02-25 9:30 ` [PATCH 6/9] dt-bindings: soc: qcom: aoss: Add SC7280 compatible Sai Prakash Ranjan
2021-02-25 19:40 ` Stephen Boyd
2021-03-06 20:53 ` Rob Herring
2021-02-25 9:30 ` [PATCH 7/9] soc: qcom: aoss: Add AOSS QMP support for SC7280 Sai Prakash Ranjan
2021-02-25 19:40 ` Stephen Boyd
2021-02-25 9:30 ` [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node Sai Prakash Ranjan
2021-02-25 19:41 ` Stephen Boyd
2021-02-26 7:51 ` Sai Prakash Ranjan
2021-02-26 18:46 ` Stephen Boyd
2021-02-27 13:56 ` Sai Prakash Ranjan
2021-03-09 5:58 ` Sibi Sankar
2021-03-23 3:38 ` Stephen Boyd
2021-03-24 7:05 ` Sibi Sankar
2021-02-25 9:30 ` [PATCH 9/9] arm64: dts: qcom: sc7280: Add Coresight support Sai Prakash Ranjan
2021-03-11 23:14 ` [PATCH 0/9] qcom/sc7280: Enable various hardware blocks on SC7280 SoC Bjorn Andersson
2021-03-14 19:05 ` Sai Prakash Ranjan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c4b7ae4dd009f563e6786f4a41f09efa38636fb6.1614244789.git.saiprakash.ranjan@codeaurora.org \
--to=saiprakash.ranjan@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=rnayak@codeaurora.org \
--cc=sibis@codeaurora.org \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).