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AJvYcCU6vC9Rz8OYEHaibIu3oB1rLOnNzbuNzpeKPkwJqLN/v6b3ebJm6+FHSEoKVIgo4VI04jKflk8V3IuBYSBZaTklypLscHTXm9m3qAax X-Gm-Message-State: AOJu0YwRgVyyhuPTtajg2LdjF14pNFDrA91g24lXeVwWc4tFHB7+Df8R 8u5FZ/umJdJ3tTxITdJeK4Ziy6uDMkhbHVpLx1vBDUTj0gsnJfxiGBHtrT1msgw= X-Google-Smtp-Source: AGHT+IF9T4xVGnEMDWOvmebwvh7RSH//MnjXmlytzIKhD9eeivlJmumrE3KnhdTbwCwawu0TsPm8Jg== X-Received: by 2002:a05:6402:4347:b0:568:1882:651f with SMTP id n7-20020a056402434700b005681882651fmr276209edc.25.1710793069043; Mon, 18 Mar 2024 13:17:49 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id g18-20020a056402091200b00568b6f73491sm3513123edz.14.2024.03.18.13.17.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Mar 2024 13:17:48 -0700 (PDT) Message-ID: Date: Mon, 18 Mar 2024 22:17:46 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver Content-Language: en-US To: Varshini.Rajendran@microchip.com, mturquette@baylibre.com, sboyd@kernel.org, Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20240223171342.669133-1-varshini.rajendran@microchip.com> <20240223172831.672953-1-varshini.rajendran@microchip.com> <01e96d4b-3038-498b-a9b2-2acac51f1d80@tuxon.dev> From: claudiu beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18.03.2024 11:25, Varshini.Rajendran@microchip.com wrote: > Hi Claudiu, > > On 11/03/24 11:28 am, claudiu beznea wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On 23.02.2024 19:28, Varshini Rajendran wrote: >>> Add a driver for the PMC clocks of sam9x7 Soc family. >>> >>> Signed-off-by: Varshini Rajendran >>> --- >>> Changes in v4: >>> - Changed variable name alloc_mem to clk_mux_buffer to be more >>> suggestive >>> - Changed description of @f structure member appropriately >>> --- >>> drivers/clk/at91/Makefile | 1 + >>> drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ >>> 2 files changed, 947 insertions(+) >>> create mode 100644 drivers/clk/at91/sam9x7.c >>> >>> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile >>> index 89061b85e7d2..8e3684ba2c74 100644 >>> --- a/drivers/clk/at91/Makefile >>> +++ b/drivers/clk/at91/Makefile [ ... ] >>> +static const struct { >>> + const char *n; >>> + const char *p; >>> + const struct clk_pll_layout *l; >>> + u8 t; >>> + const struct clk_pll_characteristics *c; >>> + unsigned long f; >>> + u8 eid; >>> +} sam9x7_plls[][PLL_ID_MAX] = { >>> + [PLL_ID_PLLA] = { >>> + { >>> + .n = "plla_fracck", >>> + .p = "mainck", >>> + .l = &plla_frac_layout, >>> + .t = PLL_TYPE_FRAC, >>> + /* >>> + * This feeds plla_divpmcck which feeds CPU. It should >>> + * not be disabled. >>> + */ >>> + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, >>> + .c = &plla_characteristics, >>> + }, >>> + >>> + { >>> + .n = "plla_divpmcck", >>> + .p = "plla_fracck", >>> + .l = &pll_divpmc_layout, >> >> You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW >> PLL freq dividers" that this has div2 but it is registered w/ a layout that >> has .div2 = 0. > > This is handled in the above plla_fracck fractional part as defined in > the plla_frac_layout. Ah, right. I missed the changes in sam9x60_frac_pll_recalc_rate().