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[2003:e9:4717:cf3f:837b:83e4:64a2:27b5]) by smtp.googlemail.com with ESMTPSA id d129sm4271268wmd.23.2021.09.30.02.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 02:02:11 -0700 (PDT) Message-ID: Subject: Re: [PATCH v1 2/2] mmc: sdhci: Use the SW timer when the HW timer cannot meet the timeout value required by the device From: Bean Huo To: Adrian Hunter , Ulf Hansson Cc: Bean Huo , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Thu, 30 Sep 2021 11:02:11 +0200 In-Reply-To: <6d57e6bd-24ba-f07e-678c-691f202549d5@intel.com> References: <20210917172727.26834-1-huobean@gmail.com> <20210917172727.26834-3-huobean@gmail.com> <93292ef4-8548-d2ba-d803-d3b40b7e6c1d@intel.com> <40e525300cd656dd17ffc89e1fcbc9a47ea90caf.camel@gmail.com> <79056ca7-bfe3-1b25-b6fd-de8a9388b75f@intel.com> <5a5db6c2eed2273a8903b5052312f039dd629401.camel@gmail.com> <5072935e-d855-7029-1ac0-0883978f66e5@intel.com> <37497369a4cf5f729e7b3e31727a7d64be5482db.camel@gmail.com> <32b753ff-6702-fa51-2df2-32ff1d955a23@intel.com> <296607ef57f3fb632107997f4edca99a5722beab.camel@gmail.com> <3078b365b5ddfad198a5c8a097f2e7edb9730e2c.camel@gmail.com> <6d57e6bd-24ba-f07e-678c-691f202549d5@intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.5-0ubuntu1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2021-09-30 at 11:59 +0300, Adrian Hunter wrote: > On 30/09/2021 11:34, Bean Huo wrote: > > Hi Adrian, > > > > > > Thanks. > > I want to give a short conclusion for our discussion: > > > > Based on your information, these sounds disable of HW timer timeout > > interrupt will make eMMC host controller malfunction, in another > > word, > > the disable of timeout interrupt will make the eMMC host cannot > > correctly provide the completion interrupt. And unless only when > > the > > SOC vendor signals that their SOC supports that the host side SW > > can > > disable this HW timeout interrupt, as TI does. > > > > I studied the SDHCI Spec, and tried to see if there is this kind of > > support statement, but not been found yet. I will check with other > > SOC > > vendors. > > > > I have one more question, if you know, please give me your > > information. > > > > I did testing on HW timer bahevior in case CQE is on. Currently, > > we > > always set the HW timer with the maximum timeout value if CQE is > > on. > > Based on my testing, the HW timer will never timeout when we enable > > CQE. I changed the HW timer value to be lower, it is the same > > result. > > Do you know that the HW timer will be inactivated in case CQE is > > on? but its timeout interrupt is still enabled. > > No I don't know how different CQE handle timeouts. Thanks anyway. Bean > > > Kind regards, > > Bean > >