From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E088CCA47D for ; Fri, 10 Jun 2022 23:20:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348857AbiFJXUm (ORCPT ); Fri, 10 Jun 2022 19:20:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236029AbiFJXUk (ORCPT ); Fri, 10 Jun 2022 19:20:40 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CADBF132753 for ; Fri, 10 Jun 2022 16:20:35 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id d19so622573lji.10 for ; Fri, 10 Jun 2022 16:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=+1KGEkwWLM43iC+5lY7oAILbV9nPk+PkPYaUeBPSvSU=; b=OZ5TGaBWVxQM1BG7nUmMRhWQAL0bYjQvzCHtYv6pljRCEtdbqyzh2WSR8NfirAf1BE 0PowjHzxVk9/i33L8CiF/ZufMvQOtZSalpnddvGcmybO/ujen0XQ2iYowO7K2O1H+F1p pOEn7Fw7aSEY+3lVQsSfEYbuf6K0bl8jWQ8dQavVd/Q2BVLvT1FG7KfTFyheVpZHLQPC lHJswhn4ESNUIGF2TqbmWTGjYoEc4xQQEzxM4tTF4m57D6wcSYdD0P7DNwmXqXX9Gktm 4Bc7LOdaT/wFPBcXkeQCwWXdSdOyUp07/y3Ya52DTEezPPov3bL8fcPpZr9PhfWVJjkj BDHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=+1KGEkwWLM43iC+5lY7oAILbV9nPk+PkPYaUeBPSvSU=; b=QYfO2R7+9eXXCY1nqAuRQZQlz0m+gpIb0Y5aVJTHWL9cZmiqGrNry6ha9csfl1bvxc qDn+hEAQQaiP4J2VCw45BVScxx02Ezlh8cEpXgcxfYTaQrJ68xfITXDI1pSXj1UpmBxh Yvt7ccEb6IxcGyL7ghg8O+57CIrprv2XXeAv6IS+yA3aRr6+ap0MdV4eVe5l3q5/Tx5g xLMinLhT6TgsOGB6ZFVL+NuF96I8QWFxKRWn2uttKHbywYAtG4bjIJwsBVz2OrQRnEu+ bSOUa1sSHzRpjuebbKGCfXRMSwiq3vAC0tRLv+AIe5NfHEtIDfgevL4Ubwrb5THD1gDE giRw== X-Gm-Message-State: AOAM533Ewj8d67RaZStkHF1T2Ivw1BR+B3cOKrlHUUsM26c+h3l6VjzB 5WgiagDUGKOcYCSUoB97u/4ZCw== X-Google-Smtp-Source: ABdhPJz9HqxCw3RkPKOT33MrJqEv4Egm/i22eg8F0ELVG+l7eXyL6eq7p9b0mPQsY6A9+1k0yXttRw== X-Received: by 2002:a05:651c:1543:b0:255:92f8:6e8b with SMTP id y3-20020a05651c154300b0025592f86e8bmr16098939ljp.489.1654903234104; Fri, 10 Jun 2022 16:20:34 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v27-20020ac2559b000000b00478d4df81f6sm35031lfg.85.2022.06.10.16.20.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jun 2022 16:20:32 -0700 (PDT) Message-ID: Date: Sat, 11 Jun 2022 02:20:31 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 2/2] arm64: dts: qcom: msm8953: add MDSS Content-Language: en-GB To: Luca Weiss , linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Vladimir Lypak , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220610225304.267508-1-luca@z3ntu.xyz> <20220610225304.267508-2-luca@z3ntu.xyz> From: Dmitry Baryshkov In-Reply-To: <20220610225304.267508-2-luca@z3ntu.xyz> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/06/2022 01:53, Luca Weiss wrote: > From: Vladimir Lypak > > Add the MDSS, MDP and DSI nodes that are found on msm8953 SoC. > > IOMMU is not added because support for it isn't yet upstream and MDSS > works fine without IOMMU on 8953. > > Signed-off-by: Vladimir Lypak > Signed-off-by: Luca Weiss Looks good, few minor nits below. > --- > arch/arm64/boot/dts/qcom/msm8953.dtsi | 202 ++++++++++++++++++++++++++ > 1 file changed, 202 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index ffc3ec2cd3bc..a2aca3d05899 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -726,6 +726,208 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 { > reg = <0x193f044 0x4>; > }; > > + mdss: mdss@1a00000 { > + compatible = "qcom,mdss"; > + > + reg = <0x1a00000 0x1000>, > + <0x1ab0000 0x1040>; > + reg-names = "mdss_phys", > + "vbif_phys"; > + > + power-domains = <&gcc MDSS_GDSC>; > + interrupts = ; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + clocks = <&gcc GCC_MDSS_AHB_CLK>, > + <&gcc GCC_MDSS_AXI_CLK>, > + <&gcc GCC_MDSS_VSYNC_CLK>; Please also add GCC_MDSS_MDP_CLK at the end of this array. It might be required to read HW_REV register. > + clock-names = "iface", > + "bus", > + "vsync"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; status = "disabled"; > + > + mdp: mdp@1a01000 { > + compatible = "qcom,mdp5"; > + reg = <0x1a01000 0x89000>; > + reg-names = "mdp_phys"; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + power-domains = <&gcc MDSS_GDSC>; > + > + clocks = <&gcc GCC_MDSS_AHB_CLK>, > + <&gcc GCC_MDSS_AXI_CLK>, > + <&gcc GCC_MDSS_MDP_CLK>, > + <&gcc GCC_MDSS_VSYNC_CLK>; > + clock-names = "iface", > + "bus", > + "core", > + "vsync"; > + > + // iommus = <&apps_iommu 0xc00 0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdp5_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdp5_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@1a94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0x1a94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + assigned-clocks = <&gcc BYTE0_CLK_SRC>, > + <&gcc PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + clocks = <&gcc GCC_MDSS_MDP_CLK>, > + <&gcc GCC_MDSS_AHB_CLK>, > + <&gcc GCC_MDSS_AXI_CLK>, > + <&gcc GCC_MDSS_BYTE0_CLK>, > + <&gcc GCC_MDSS_PCLK0_CLK>, > + <&gcc GCC_MDSS_ESC0_CLK>; > + clock-names = "mdp_core", > + "iface", > + "bus", > + "byte", > + "pixel", > + "core"; > + > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&mdp5_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: dsi-phy@1a94400 { > + compatible = "qcom,dsi-phy-14nm-8953"; > + reg = <0x1a94400 0x100>, > + <0x1a94500 0x300>, > + <0x1a94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; status = "disabled"; > + > + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; > + clock-names = "iface", "ref"; > + }; > + > + dsi1: dsi@1a96000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0x1a96000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <5>; > + > + assigned-clocks = <&gcc BYTE1_CLK_SRC>, > + <&gcc PCLK1_CLK_SRC>; > + assigned-clock-parents = <&dsi1_phy 0>, > + <&dsi1_phy 1>; > + > + clocks = <&gcc GCC_MDSS_MDP_CLK>, > + <&gcc GCC_MDSS_AHB_CLK>, > + <&gcc GCC_MDSS_AXI_CLK>, > + <&gcc GCC_MDSS_BYTE1_CLK>, > + <&gcc GCC_MDSS_PCLK1_CLK>, > + <&gcc GCC_MDSS_ESC1_CLK>; > + clock-names = "mdp_core", > + "iface", > + "bus", > + "byte", > + "pixel", > + "core"; > + > + phys = <&dsi1_phy>; > + phy-names = "dsi"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi1_in: endpoint { > + remote-endpoint = <&mdp5_intf2_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi1_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi1_phy: dsi-phy@1a96400 { > + compatible = "qcom,dsi-phy-14nm-8953"; > + reg = <0x1a96400 0x100>, > + <0x1a96500 0x300>, > + <0x1a96800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + }; > + > spmi_bus: spmi@200f000 { > compatible = "qcom,spmi-pmic-arb"; > reg = <0x200f000 0x1000>, -- With best wishes Dmitry