From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FCA2C433F5 for ; Thu, 18 Nov 2021 13:26:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC25E6113D for ; Thu, 18 Nov 2021 13:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231208AbhKRN27 (ORCPT ); Thu, 18 Nov 2021 08:28:59 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:52885 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230512AbhKRN27 (ORCPT ); Thu, 18 Nov 2021 08:28:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1637241958; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kb1ScM+tPjpaRtxM4KUni8Ao9s67vbqfcmBg158Ebpk=; b=fjshLGupEPAtqh8XNOhA60MxDmPi4LA2FFTOmmcz8mTSRRtQMN8+UbNCAs7Sy9uSY2v/Cs QB7NkrCzSrrUWojQK5AR2Il0tRRuTyu80nKO3aNf9TTm4MEWrLlf3YW1JA13edqesE/LyA m6t4rTJsk+CS45BOKU7Dck3pYFWx9EM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-287-urWffV7eM2mCNtKSCJvgSA-1; Thu, 18 Nov 2021 08:25:55 -0500 X-MC-Unique: urWffV7eM2mCNtKSCJvgSA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AB30018D6A36; Thu, 18 Nov 2021 13:25:53 +0000 (UTC) Received: from [10.39.192.245] (unknown [10.39.192.245]) by smtp.corp.redhat.com (Postfix) with ESMTP id 80A6C1B5C2; Thu, 18 Nov 2021 13:25:33 +0000 (UTC) Message-ID: Date: Thu, 18 Nov 2021 14:25:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH] KVM: x86/svm: Add module param to control PMU virtualization Content-Language: en-US To: Like Xu , Maxim Levitsky Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20211117080304.38989-1-likexu@tencent.com> From: Paolo Bonzini In-Reply-To: <20211117080304.38989-1-likexu@tencent.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/17/21 09:03, Like Xu wrote: > From: Like Xu > > For Intel, the guest PMU can be disabled via clearing the PMU CPUID. > For AMD, all hw implementations support the base set of four > performance counters, with current mainstream hardware indicating > the presence of two additional counters via X86_FEATURE_PERFCTR_CORE. > > In the virtualized world, the AMD guest driver may detect > the presence of at least one counter MSR. Most hypervisor > vendors would introduce a module param (like lbrv for svm) > to disable PMU for all guests. > > Another control proposal per-VM is to pass PMU disable information > via MSR_IA32_PERF_CAPABILITIES or one bit in CPUID Fn4000_00[FF:00]. > Both of methods require some guest-side changes, so a module > parameter may not be sufficiently granular, but practical enough. > > Signed-off-by: Like Xu > --- > arch/x86/kvm/cpuid.c | 2 +- > arch/x86/kvm/svm/pmu.c | 4 ++++ > arch/x86/kvm/svm/svm.c | 11 +++++++++++ > arch/x86/kvm/svm/svm.h | 1 + > 4 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 2d70edb0f323..647af2a184ad 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -487,7 +487,7 @@ void kvm_set_cpu_caps(void) > F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | > F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | > 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | > - F(TOPOEXT) | F(PERFCTR_CORE) > + F(TOPOEXT) | 0 /* PERFCTR_CORE */ > ); > > kvm_cpu_cap_mask(CPUID_8000_0001_EDX, > diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c > index fdf587f19c5f..a0bcf0144664 100644 > --- a/arch/x86/kvm/svm/pmu.c > +++ b/arch/x86/kvm/svm/pmu.c > @@ -16,6 +16,7 @@ > #include "cpuid.h" > #include "lapic.h" > #include "pmu.h" > +#include "svm.h" > > enum pmu_type { > PMU_TYPE_COUNTER = 0, > @@ -100,6 +101,9 @@ static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr, > { > struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); > > + if (!pmuv) > + return NULL; > + > switch (msr) { > case MSR_F15H_PERF_CTL0: > case MSR_F15H_PERF_CTL1: > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index 21bb81710e0f..062e48c191ee 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -190,6 +190,10 @@ module_param(vgif, int, 0444); > static int lbrv = true; > module_param(lbrv, int, 0444); > > +/* enable/disable PMU virtualization */ > +bool pmuv = true; > +module_param(pmuv, bool, 0444); > + > static int tsc_scaling = true; > module_param(tsc_scaling, int, 0444); > > @@ -952,6 +956,10 @@ static __init void svm_set_cpu_caps(void) > boot_cpu_has(X86_FEATURE_AMD_SSBD)) > kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); > > + /* AMD PMU PERFCTR_CORE CPUID */ > + if (pmuv && boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) > + kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE); > + > /* CPUID 0x8000001F (SME/SEV features) */ > sev_set_cpu_caps(); > } > @@ -1085,6 +1093,9 @@ static __init int svm_hardware_setup(void) > pr_info("LBR virtualization supported\n"); > } > > + if (!pmuv) > + pr_info("PMU virtualization is disabled\n"); > + > svm_set_cpu_caps(); > > /* > diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h > index 0d7bbe548ac3..08e1c19ffbdf 100644 > --- a/arch/x86/kvm/svm/svm.h > +++ b/arch/x86/kvm/svm/svm.h > @@ -32,6 +32,7 @@ > extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; > extern bool npt_enabled; > extern bool intercept_smi; > +extern bool pmuv; > > /* > * Clean bits in VMCB. > Queued, thanks - just changed the parameter name to "pmu". Paolo