From: Finley Xiao <finley.xiao@rock-chips.com>
To: Rob Herring <robh@kernel.org>
Cc: srinivas.kandagatla@linaro.org, maxime.ripard@free-electrons.com,
heiko@sntech.de, frowand.list@gmail.com, sre@kernel.org,
dbaryshkov@gmail.com, dwmw2@infradead.org, mark.rutland@arm.com,
khilman@kernel.org, nm@ti.com, rjw@rjwysocki.net,
viresh.kumar@linaro.org, sboyd@codeaurora.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
wxt@rock-chips.com, jay.xu@rock-chips.com,
rocky.hao@rock-chips.com, tim.chen@rock-chips.com,
tony.xie@rock-chips.com, ulysses.huang@rock-chips.com,
lin.huang@rock-chips.com
Subject: Re: [PATCH v1 3/3] PM / AVS: rockchip-cpu-avs: add driver handling Rockchip cpu avs
Date: Tue, 23 Aug 2016 12:10:27 +0800 [thread overview]
Message-ID: <c853c8fd-285a-603d-b294-750cdbf7f200@rock-chips.com> (raw)
In-Reply-To: <20160819133636.GA26913@rob-hp-laptop>
在 2016/8/19 21:36, Rob Herring 写道:
> On Tue, Aug 16, 2016 at 10:38:59AM +0800, Finlye Xiao wrote:
>> From: Finley Xiao <finley.xiao@rock-chips.com>
>>
>> This patch supports adjusting opp's voltage according to leakage
>>
>> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
>> ---
>> .../devicetree/bindings/power/rockchip-cpu-avs.txt | 37 +++
>> drivers/power/avs/Kconfig | 8 +
>> drivers/power/avs/Makefile | 1 +
>> drivers/power/avs/rockchip-cpu-avs.c | 314 +++++++++++++++++++++
>> 4 files changed, 360 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/power/rockchip-cpu-avs.txt
>> create mode 100644 drivers/power/avs/rockchip-cpu-avs.c
>>
>> diff --git a/Documentation/devicetree/bindings/power/rockchip-cpu-avs.txt b/Documentation/devicetree/bindings/power/rockchip-cpu-avs.txt
>> new file mode 100644
>> index 0000000..90f6b08
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/power/rockchip-cpu-avs.txt
>> @@ -0,0 +1,37 @@
>> +Rockchip cpu avs device tree bindings
>> +-------------------------------------
>> +
>> +Under the same frequency, the operating voltage tends to decrease with
>> +increasing leakage. so it is necessary to adjust opp's voltage according
>> +to leakage for power.
>> +
>> +
>> +Required properties:
>> +- compatible: Should be one of the following.
>> + - "rockchip,rk3399-cpu-avs" - for RK3399 SoCs.
>> +- leakage-volt-<name>: Named leakage-volt property. At runtime, the
>> + platform can find a cpu's cluster_id according to it's cpu_id and match
>> + leakage-volt-<name> property. The property is an array of 3-tuples
>> + items, and each item consists of leakage and voltage like
>> + <min-leakage-mA max-leakage-mA vol-uV>.
>> + min-leakage: minimum leakage in mA.
>> + max-leakage: maximum leakage in mA.
>> + vol: voltage in microvolt.
> How do you determine these values? When do they vary?
How do you determine these values?
run antutu-benchmark
leakage freq min_volt
30mA 1608MHz 1025mV
40mA 1608MHz 1000mV
50mA 1608MHz 975mV
From the table, we see the min_volt decrease with increasing leakage.
So we can set the default opp-microvolt 1025mV for 1608MHz,
and add an leakage_volt_cluster0 property as follows.
leakage_volt_cluster0 = <
/* min(mA) max(mA) volt(uV)*/
0 40 0
41 50 (-25000)
51 254 (-50000)
>;
If the leakage is between 41mA and 50mA,the opp-microvolt will subtract 25mV。
If the leakage is between 41mA and 50mA,the opp-microvolt will subtract 50mV。
When do they vary?
From the code,
cpufreq_online
--cpufreq_driver->init(policy); /* add new opp table */
--blocking_notifier_call_chain(&cpufreq_policy_notifier_list,
CPUFREQ_START, policy);
--cpufreq_init_policy
----cpufreq_set_policy
--------__cpufreq_governor(policy, CPUFREQ_GOV_START);
The cpu's opp table is added in the init function(cpufreq_init),and I will
register a cpufreq notifier, once the first cpu of cluster is onlined,
my notifer will be called, and if the event is CPUFREQ_START,it will modify
the opp-microvolt according to leakage_volt_cluster0.
>> +
>> +Example:
>> +
>> + cpu_avs: cpu-avs {
>> + compatible = "rockchip,rk3399-cpu-avs";
> This isn't really a hardware block. For the same reasons we don't have
> cpufreq nodes. So I don't think this belongs in DT.
if I delete the compatible property like the thermal-zones node, is it allowed?
cpu_avs: cpu-avs {
leakage_volt_cluster0 = <
/* min(mA) max(mA) volt(uV)*/
0 40 0
41 50 (-25000)
51 254 (-50000)
>;
leakage_volt_cluster1 = <
/* min(mA) max(mA) volt(uV)*/
0 40 0
41 50 (-25000)
51 254 (-50000)
>;
}
>
> Rob
>
>
>
--
Finley
next prev parent reply other threads:[~2016-08-23 4:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-16 2:38 [PATCH v1 0/3] PM / AVS: add Rockchip cpu avs Finlye Xiao
2016-08-16 2:38 ` [PATCH v1 1/3] nvmem: rockchip-efuse: Change initcall to subsys Finlye Xiao
2016-08-16 2:38 ` [PATCH v1 2/3] of: Add support for reading a s32 from a multi-value property Finlye Xiao
2016-08-16 12:09 ` Heiko Stübner
2016-08-19 14:15 ` David Woodhouse
2016-08-19 20:41 ` Heiko Stuebner
2016-08-19 20:47 ` David Woodhouse
2016-08-22 14:07 ` Finley Xiao
2016-08-22 14:51 ` Mark Rutland
2016-08-16 2:38 ` [PATCH v1 3/3] PM / AVS: rockchip-cpu-avs: add driver handling Rockchip cpu avs Finlye Xiao
2016-08-16 5:13 ` kbuild test robot
2016-08-16 17:24 ` Heiko Stübner
2016-08-17 13:59 ` Finley Xiao
2016-08-19 13:36 ` Rob Herring
2016-08-23 4:10 ` Finley Xiao [this message]
2016-08-23 9:03 ` Heiko Stübner
2016-08-23 9:29 ` Finley Xiao
2016-09-08 16:56 ` Rob Herring
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