From 52e56378721f2e0ffde337f38db96a92d1870dc7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 30 Oct 2018 12:14:27 +0100 Subject: [PATCH] ASoC: intel: cht_bsw_max98090_ti: Also enable/disable pmc_plt_clk_0 Testing has shown that some boards not only use pmc_plt_clk_3 but also use pmc_plt_clk_0. This commit makes us also get and enable/disable pmc_plt_clk_0 as necessary, fixing sound not working on these boards. Signed-off-by: Hans de Goede --- sound/soc/intel/boards/cht_bsw_max98090_ti.c | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/sound/soc/intel/boards/cht_bsw_max98090_ti.c b/sound/soc/intel/boards/cht_bsw_max98090_ti.c index db6976f4ddaa..750ac2160200 100644 --- a/sound/soc/intel/boards/cht_bsw_max98090_ti.c +++ b/sound/soc/intel/boards/cht_bsw_max98090_ti.c @@ -36,7 +36,7 @@ #define CHT_CODEC_DAI "HiFi" struct cht_mc_private { - struct clk *mclk; + struct clk_bulk_data clks[2]; struct snd_soc_jack jack; bool ts3a227e_present; }; @@ -57,14 +57,14 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, } if (SND_SOC_DAPM_EVENT_ON(event)) { - ret = clk_prepare_enable(ctx->mclk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(ctx->clks), ctx->clks); if (ret < 0) { dev_err(card->dev, "could not configure MCLK state"); return ret; } } else { - clk_disable_unprepare(ctx->mclk); + clk_bulk_disable_unprepare(ARRAY_SIZE(ctx->clks), ctx->clks); } return 0; @@ -229,11 +229,11 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) * to disable a clock that has not been enabled, * we need to enable the clock first. */ - ret = clk_prepare_enable(ctx->mclk); + ret = clk_prepare_enable(ctx->clks[0].clk); if (!ret) - clk_disable_unprepare(ctx->mclk); + clk_disable_unprepare(ctx->clks[0].clk); - ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); + ret = clk_set_rate(ctx->clks[0].clk, CHT_PLAT_CLK_3_HZ); if (ret) dev_err(runtime->dev, "unable to set MCLK rate\n"); @@ -411,12 +411,12 @@ static int snd_cht_mc_probe(struct platform_device *pdev) snd_soc_card_cht.dev = &pdev->dev; snd_soc_card_set_drvdata(&snd_soc_card_cht, drv); - drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); - if (IS_ERR(drv->mclk)) { - dev_err(&pdev->dev, - "Failed to get MCLK from pmc_plt_clk_3: %ld\n", - PTR_ERR(drv->mclk)); - return PTR_ERR(drv->mclk); + drv->clks[0].id = "pmc_plt_clk_3"; /* Standard codec clk */ + drv->clks[1].id = "pmc_plt_clk_0"; /* Extra clk used on some boards */ + ret_val = devm_clk_bulk_get(&pdev->dev, 2, drv->clks); + if (ret_val) { + dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret_val); + return ret_val; } ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht); -- 2.19.0