From: "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>
To: Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: robh@kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
andriy.shevchenko@intel.com, qi-ming.wu@intel.com,
yixin.zhu@linux.intel.com, cheol.yong.kim@intel.com,
rtanwar <rahul.tanwar@intel.com>
Subject: Re: [PATCH v8 2/2] clk: intel: Add CGU clock driver for a new SoC
Date: Wed, 27 May 2020 11:53:14 +0800 [thread overview]
Message-ID: <c91ec0e0-5a16-2e28-dae0-4219f5f5340f@linux.intel.com> (raw)
In-Reply-To: <159054541310.88029.5777794695153819198@swboyd.mtv.corp.google.com>
Hi Stephen,
On 27/5/2020 10:10 am, Stephen Boyd wrote:
> Quoting Rahul Tanwar (2020-04-16 22:54:47)
>> diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
>> new file mode 100644
>> index 000000000000..802a7fa88535
>> --- /dev/null
>> +++ b/drivers/clk/x86/clk-cgu.c
>> @@ -0,0 +1,636 @@
> [...]
>> + ctx->membase = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(ctx->membase))
>> + return PTR_ERR(ctx->membase);
>> +
>> + ctx->np = np;
>> + ctx->dev = dev;
>> + spin_lock_init(&ctx->lock);
>> +
>> + ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
>> + ARRAY_SIZE(lgm_pll_clks));
>> + if (ret)
>> + return ret;
>> +
>> + ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
>> + ARRAY_SIZE(lgm_branch_clks));
>> + if (ret)
>> + return ret;
>> +
>> + ret = lgm_clk_register_ddiv(ctx, lgm_ddiv_clks,
>> + ARRAY_SIZE(lgm_ddiv_clks));
>> + if (ret)
>> + return ret;
>> +
>> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> + &ctx->clk_data);
>> + if (ret)
>> + return ret;
> Are any of the clks unregistered on failure? It looks like devm_ isn't
> used for registration so nothing can be undone? Please fix this in a
> future patch.
Thanks a lot for accepting the patch series. I went through all of your
comments and i agree with all of them. Will fix it & address other
review concerns in a future patch once 5.8 is released.
Regards,
Rahul
next prev parent reply other threads:[~2020-05-27 3:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-17 5:54 [PATCH v8 0/2] clk: intel: Add a new driver for a new clock controller IP Rahul Tanwar
2020-04-17 5:54 ` [PATCH v8 1/2] dt-bindings: clk: intel: Add bindings document & header file for CGU Rahul Tanwar
2020-05-27 1:48 ` Stephen Boyd
2020-04-17 5:54 ` [PATCH v8 2/2] clk: intel: Add CGU clock driver for a new SoC Rahul Tanwar
2020-05-27 2:10 ` Stephen Boyd
2020-05-27 3:53 ` Tanwar, Rahul [this message]
2020-05-27 2:10 ` Stephen Boyd
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