Re: [PATCH 1/7] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

From: Chanwoo Choi <cw00.choi@samsung.com>
To: Sam Protsenko <semen.protsenko@linaro.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Rob Herring <robh+dt@kernel.org>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Jaewon Kim <jaewon02.kim@samsung.com>,
	Chanho Park <chanho61.park@samsung.com>,
	David Virag <virag.david003@gmail.com>,
	Youngmin Nam <youngmin.nam@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Daniel Palmer <daniel@0x0f.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks
Date: Thu, 16 Dec 2021 16:03:42 +0900	[thread overview]
Message-ID: <c9e6210b-3eda-c05c-abfb-e4432cf3b83d@samsung.com> (raw)
In-Reply-To: <20211215160906.17451-2-semen.protsenko@linaro.org>

On 12/16/21 1:09 AM, Sam Protsenko wrote:
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
> 
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
>  include/dt-bindings/clock/exynos850.h | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 8aa5e82af0d3..0b6a3c6a7c90 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -82,7 +82,10 @@
>  #define CLK_GOUT_I3C_PCLK		19
>  #define CLK_GOUT_I3C_SCLK		20
>  #define CLK_GOUT_SPEEDY_PCLK		21
> -#define APM_NR_CLK			22
> +#define CLK_GOUT_GPIO_ALIVE_PCLK	22
> +#define CLK_GOUT_PMU_ALIVE_PCLK		23
> +#define CLK_GOUT_SYSREG_APM_PCLK	24
> +#define APM_NR_CLK			25
>  
>  /* CMU_CMGP */
>  #define CLK_RCO_CMGP			1
> @@ -99,7 +102,8 @@
>  #define CLK_GOUT_CMGP_USI0_PCLK		12
>  #define CLK_GOUT_CMGP_USI1_IPCLK	13
>  #define CLK_GOUT_CMGP_USI1_PCLK		14
> -#define CMGP_NR_CLK			15
> +#define CLK_GOUT_SYSREG_CMGP_PCLK	15
> +#define CMGP_NR_CLK			16
>  
>  /* CMU_HSI */
>  #define CLK_MOUT_HSI_BUS_USER		1
> @@ -167,7 +171,9 @@
>  #define CLK_GOUT_MMC_EMBD_SDCLKIN	10
>  #define CLK_GOUT_SSS_ACLK		11
>  #define CLK_GOUT_SSS_PCLK		12
> -#define CORE_NR_CLK			13
> +#define CLK_GOUT_GPIO_CORE_PCLK		13
> +#define CLK_GOUT_SYSREG_CORE_PCLK	14
> +#define CORE_NR_CLK			15
>  
>  /* CMU_DPU */
>  #define CLK_MOUT_DPU_USER		1
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics