From: Vladimir Murzin <vladimir.murzin@arm.com>
To: Christoph Hellwig <hch@lst.de>, Palmer Dabbelt <palmer@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 17/17] riscv: add nommu support
Date: Tue, 11 Jun 2019 11:32:38 +0100 [thread overview]
Message-ID: <cbf88fe0-94a6-b559-2b64-c725f236b683@arm.com> (raw)
In-Reply-To: <20190610221621.10938-18-hch@lst.de>
On 6/10/19 11:16 PM, Christoph Hellwig wrote:
> Most of the patch is just stubbing out code not needed without page
> tables, but there is an interesting detail in the signals implementation:
>
> - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO
> entry point, but the ELF VDSO is not supported for nommu Linux.
> We instead copy the code to call the syscall onto the stack.
On ARM we perform I/D cache synchronization after stack manipulation.
OTOH, ARM port of uClibc provides SA_RESTORER with intention to avoid
manipulation with stack and cache maintenance operations (yet kernel
still performs such manipulation, IIUC, for backward compatibility)
Cheers
Vladimir
next prev parent reply other threads:[~2019-06-11 10:32 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 22:16 RISC-V nommu support Christoph Hellwig
2019-06-10 22:16 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-11 10:11 ` Vladimir Murzin
2019-06-10 22:16 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-11 10:15 ` Vladimir Murzin
2019-06-11 14:18 ` Christoph Hellwig
2019-06-11 14:36 ` Vladimir Murzin
2019-06-14 9:48 ` Christoph Hellwig
2019-06-10 22:16 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-11 10:19 ` Vladimir Murzin
2019-06-10 22:16 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-06-10 22:16 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-06-10 22:16 ` [PATCH 06/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-06-10 22:16 ` [PATCH 07/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-10 22:16 ` [PATCH 08/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-06-10 22:16 ` [PATCH 09/17] riscv: improve the default power off implementation Christoph Hellwig
2019-06-10 22:16 ` [PATCH 10/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-10 22:16 ` [PATCH 11/17] riscv: read hart ID from mhartid on boot Christoph Hellwig
2019-06-10 22:16 ` [PATCH 12/17] riscv: provide native clint access for M-mode Christoph Hellwig
2019-06-10 22:16 ` [PATCH 13/17] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 14/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 15/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 16/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-06-11 10:32 ` Vladimir Murzin [this message]
2019-06-11 12:44 ` David Hildenbrand
2019-06-24 5:42 RISC-V nommu support v2 Christoph Hellwig
2019-06-24 5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-07-12 14:52 ` Vladimir Murzin
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