From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 860E1C43381 for ; Sat, 30 Mar 2019 02:40:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 55784218D8 for ; Sat, 30 Mar 2019 02:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730505AbfC3Ckp (ORCPT ); Fri, 29 Mar 2019 22:40:45 -0400 Received: from mga04.intel.com ([192.55.52.120]:60113 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730184AbfC3Cko (ORCPT ); Fri, 29 Mar 2019 22:40:44 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 19:40:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,287,1549958400"; d="p7s'?scan'208";a="311638495" Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by orsmga005.jf.intel.com with ESMTP; 29 Mar 2019 19:40:42 -0700 Received: from orsmsx113.amr.corp.intel.com (10.22.240.9) by ORSMSX109.amr.corp.intel.com (10.22.240.7) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 29 Mar 2019 19:40:43 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.11]) by ORSMSX113.amr.corp.intel.com ([169.254.9.249]) with mapi id 14.03.0415.000; Fri, 29 Mar 2019 19:40:42 -0700 From: "Pandruvada, Srinivas" To: "Yazen.Ghannam@amd.com" , "linux-kernel@vger.kernel.org" , "devel@acpica.org" , "Janakarajan.Natarajan@amd.com" , "linux-acpi@vger.kernel.org" , "linux-pm@vger.kernel.org" CC: "lenb@kernel.org" , "viresh.kumar@linaro.org" , "Moore, Robert" , "Schmauss, Erik" , "rjw@rjwysocki.net" Subject: Re: [PATCH 5/6] acpi/cppc: Add support for optional CPPC registers Thread-Topic: [PATCH 5/6] acpi/cppc: Add support for optional CPPC registers Thread-Index: AQHU5LR0lnkbassgoEK1gi6uIOOyFaYjhPcAgABq5IA= Date: Sat, 30 Mar 2019 02:40:41 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.254.191.133] Content-Type: multipart/signed; micalg=sha-1; protocol="application/x-pkcs7-signature"; boundary="=-3puxkU1l2a00ggyCdCtN" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-3puxkU1l2a00ggyCdCtN Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2019-03-29 at 20:18 +0000, Ghannam, Yazen wrote: > > -----Original Message----- > > From: linux-acpi-owner@vger.kernel.org < > > linux-acpi-owner@vger.kernel.org> On Behalf Of Pandruvada, Srinivas > > Sent: Wednesday, March 27, 2019 10:48 AM > > To: linux-kernel@vger.kernel.org; devel@acpica.org; Natarajan, > > Janakarajan ; linux- > > acpi@vger.kernel.org; linux-pm@vger.kernel.org > > Cc: Ghannam, Yazen ; lenb@kernel.org;=20 > > viresh.kumar@linaro.org; Moore, Robert > > ; Schmauss, Erik ; > > rjw@rjwysocki.net > > Subject: Re: [PATCH 5/6] acpi/cppc: Add support for optional CPPC > > registers > >=20 > > On Fri, 2019-03-22 at 20:26 +0000, Natarajan, Janakarajan wrote: > > > From: Yazen Ghannam > > >=20 > > > Newer AMD processors support a subset of the optional CPPC > > > registers. > > > Create show, store and helper routines for supported CPPC > > > registers. > > >=20 > > > Signed-off-by: Yazen Ghannam > > > [ carved out into a patch, cleaned up, productized ] > > > Signed-off-by: Janakarajan Natarajan < > > > Janakarajan.Natarajan@amd.com> > > >=20 > >=20 > > [..] > >=20 > > > + /* desired_perf is the only mandatory value in perf_ctrls */ > > > + if (cpc_read(cpu, desired_reg, &desired)) > > > + ret =3D -EFAULT; > > > + > > > + if (CPC_SUPPORTED(max_reg) && cpc_read(cpu, max_reg, &max)) > > > + ret =3D -EFAULT; > > > + > >=20 > > We should create and use different macro other than CPPC_SUPPORTED. > > CPC_SUPPORTED doesn't validate the correctness of object type for a > > field. For example "Maximum Performance Register" can only be > > buffer > > not integer. In this way invalid field definitions can be ignored. > >=20 >=20 > So create something like "CPPC_SUPPORTED_BUFFER" for buffer-only > registers? >=20 > And then buffer/integer registers will continue to use > "CPPC_SUPPORTED". >=20 > These seem to be the only two cases at this time. Is this okay? Yes. Thanks, Srinivas >=20 > Thanks, > Yazen >=20 > >=20 > > > + if (CPC_SUPPORTED(min_reg) && cpc_read(cpu, min_reg, &min)) > > > + ret =3D -EFAULT; > > > + > > > + if (CPC_SUPPORTED(energy_reg) && cpc_read(cpu, energy_reg, > > > &energy)) > > > + ret =3D -EFAULT; > > > + > > > + if (CPC_SUPPORTED(auto_sel_enable_reg) && > > > + cpc_read(cpu, auto_sel_enable_reg, &auto_sel_enable)) > > > + ret =3D -EFAULT; > > > + > >=20 > > Here it is fine to use CPC_SUPPORTED as the "Autonomous Selection > > Enable" can be both integer and buffer. > >=20 > > Thanks, > > Srinivas >=20 >=20 --=-3puxkU1l2a00ggyCdCtN Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIIKhTCCBOsw ggPToAMCAQICEDabxALowUBS+21KC0JI8fcwDQYJKoZIhvcNAQEFBQAwbzELMAkGA1UEBhMCU0Ux FDASBgNVBAoTC0FkZFRydXN0IEFCMSYwJAYDVQQLEx1BZGRUcnVzdCBFeHRlcm5hbCBUVFAgTmV0 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