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Thu, 13 Feb 2020 00:42:57 -0800 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01D8gqlV020865; Thu, 13 Feb 2020 00:42:52 -0800 Received: from [172.30.17.107] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j2A5E-0008Uv-1d; Thu, 13 Feb 2020 00:42:52 -0800 Subject: Re: [PATCH 3/7] microblaze: Define SMP safe bit operations To: Peter Zijlstra , Michal Simek Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com, arnd@arndb.de, Stefan Asserhall , Greg Kroah-Hartman , Masahiro Yamada , Will Deacon References: <6a052c943197ed33db09ad42877e8a2b7dad6b96.1581522136.git.michal.simek@xilinx.com> <20200212155309.GA14973@hirez.programming.kicks-ass.net> From: Michal Simek Message-ID: Date: Thu, 13 Feb 2020 09:42:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200212155309.GA14973@hirez.programming.kicks-ass.net> Content-Type: text/plain; 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X-Forefront-PRVS: 031257FE13 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WoKtdMFz82wT/WNthEgTpJKW0vUCcy3KGgRh8+VclBVQtmVer5iZWRWWCwMpY07CaYa1PthuPW16iybXKl3qwsy4pFSZ4S1jRzy25zgoAgKyD2Jax+MWVaIOcOvpSVLyrR8eVwcGpHZZcJeZabmeCgQS+MJYX0zM2Kjjg/h5IrQK8yLdtm9bZdL+BffCr3jeXuGrHU1BI/q1OC/2p1bHu4QnqLNDue5ymJ8BN5qBxEjoxfRjl6Z7ww23EEtLpBiGM8o1L+ROLhQX4dM4a6MkaJn6sqLfHESc1WF530oxU4RJwkDf6GygzcMUgQzMqKKLb1tM13RbZljou11kgyx8UbmI4ucHQU8PQg1cl9dLXe+uwSHCDb2go7Cc7MyND8rSjHKQP+Cz6RYJ52SFTs6rwpycRBmtsrjyqukVXLGvqM1vJj5Y/ktdD/u/Wg9EsaoU X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 08:43:03.3288 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8312dd5d-d76c-4095-4ec7-08d7b060bd3c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB7035 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12. 02. 20 16:53, Peter Zijlstra wrote: > On Wed, Feb 12, 2020 at 04:42:25PM +0100, Michal Simek wrote: >> From: Stefan Asserhall >> >> For SMP based system there is a need to have proper bit operations. >> Microblaze is using exclusive load and store instructions. >> >> Signed-off-by: Stefan Asserhall >> Signed-off-by: Michal Simek > >> +/* >> + * clear_bit doesn't imply a memory barrier >> + */ >> +#define smp_mb__before_clear_bit() smp_mb() >> +#define smp_mb__after_clear_bit() smp_mb() > > These macros no longer exist. ok. Easy to remove. > > Also, might I draw your attention to: > > include/asm-generic/bitops/atomic.h > > This being a ll/sc arch, I'm thinking that if you do your atomic_t > implementation right, the generic atomic bitop code should be near > optimal. > Based on my look it looks like that I can replace implementations in this file by sourcing which will be using atomic operations. #include #include Correct? Would be good to run any testsuite to prove that all operations works as expected. Is there any testsuite I can use to confirm it? Thanks, Michal