From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1640DC433EF for ; Wed, 18 May 2022 13:48:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238147AbiERNsh (ORCPT ); Wed, 18 May 2022 09:48:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238289AbiERNsZ (ORCPT ); Wed, 18 May 2022 09:48:25 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8852B1C12DD; Wed, 18 May 2022 06:48:22 -0700 (PDT) Received: from fraeml743-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4L3DkB0XFQz687Z6; Wed, 18 May 2022 21:44:34 +0800 (CST) Received: from lhreml724-chm.china.huawei.com (10.201.108.75) by fraeml743-chm.china.huawei.com (10.206.15.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 18 May 2022 15:48:20 +0200 Received: from [10.47.24.102] (10.47.24.102) by lhreml724-chm.china.huawei.com (10.201.108.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 18 May 2022 14:48:18 +0100 Message-ID: Date: Wed, 18 May 2022 14:48:17 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs To: Robin Murphy , Nick Forrington , , , CC: Will Deacon , Mathieu Poirier , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , "Namhyung Kim" , Andi Kleen , Kajol Jain , James Clark , Andrew Kilroy References: <20220510104758.64677-1-nick.forrington@arm.com> <28509191-3a45-de6d-f5bc-a8e7331c0a9e@huawei.com> <5773b630-8159-1eba-481a-1bf3c406c055@arm.com> From: John Garry In-Reply-To: <5773b630-8159-1eba-481a-1bf3c406c055@arm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.47.24.102] X-ClientProxiedBy: lhreml733-chm.china.huawei.com (10.201.108.84) To lhreml724-chm.china.huawei.com (10.201.108.75) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/05/2022 13:32, Robin Murphy wrote: >> If we were to add to arm32/arm then the common event numbers and maybe >> other JSONs in future would need to be duplicated. >> >> Would there be any reason to add to arm32/arm apart to from being >> strictly proper? Maybe if lots of other 32b support for other vendors >> came along then it could make sense (to separate them out). > > That's the heart of the question, really. At best it seems unnecessarily > confusing as-is. I think it comes down to the first core supported was TX2 and the build system relies on the target arch to decide which arch from pmu-events/arch to compile. > AFAICS either the naming isn't functional, wherein it > would potentially make the most sense to rename the whole thing > "pmu-events/arch/arm" if it's merely for categorising Arm architectures > in general, or it is actually tied to the host triplet, in which case > the above patches are most likely useless. Today ARCH=arm has no pmu-events support. I think that it should be easy to add plumbing for that. It becomes more tricky with supporting a single "arm" folder. But then do people really care enough about pmu-events for these 32b cores? Until now, it seems not. > > I'd agree that there doesn't seem much point in trying to separate > things along relatively arbitrary lines if it *isn't* functionally > necessary - the PMUv2 common events look to be a straightforward subset > of the PMUv3 ones, but then there's Cortex-A32 anyway, plus most of the > already-supported CPUs could equally run an AArch32 perf tool as well. Sure, we should have these 32b cores supported for ARCH=arm if they are supported for ARCH=arm64. But then does it even make sense to have A7 support in arch/arm64? Thanks, John