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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.googlemail.com with ESMTPSA id d15sm14767385ejw.143.2022.02.01.04.27.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Feb 2022 04:27:16 -0800 (PST) Message-ID: Date: Tue, 1 Feb 2022 13:27:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH kvm/queue v2 2/3] perf: x86/core: Add interface to query perfmon_event_map[] directly Content-Language: en-US To: Like Xu , Jim Mattson , Peter Zijlstra Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu References: <20220117085307.93030-1-likexu@tencent.com> <20220117085307.93030-3-likexu@tencent.com> From: Paolo Bonzini In-Reply-To: <20220117085307.93030-3-likexu@tencent.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/17/22 09:53, Like Xu wrote: > From: Like Xu > > Currently, we have [intel|knc|p4|p6]_perfmon_event_map on the Intel > platforms and amd_[f17h]_perfmon_event_map on the AMD platforms. > > Early clumsy KVM code or other potential perf_event users may have > hard-coded these perfmon_maps (e.g., arch/x86/kvm/svm/pmu.c), so > it would not make sense to program a common hardware event based > on the generic "enum perf_hw_id" once the two tables do not match. > > Let's provide an interface for callers outside the perf subsystem to get > the counter config based on the perfmon_event_map currently in use, > and it also helps to save bytes. > > Cc: Peter Zijlstra > Signed-off-by: Like Xu > --- > arch/x86/events/core.c | 9 +++++++++ > arch/x86/include/asm/perf_event.h | 2 ++ > 2 files changed, 11 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 38b2c779146f..751048f4cc97 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -693,6 +693,15 @@ void x86_pmu_disable_all(void) > } > } > > +u64 perf_get_hw_event_config(int perf_hw_id) > +{ > + if (perf_hw_id < x86_pmu.max_events) > + return x86_pmu.event_map(perf_hw_id); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(perf_get_hw_event_config); > + > struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) > { > return static_call(x86_pmu_guest_get_msrs)(nr); > diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h > index 8fc1b5003713..d1e325517b74 100644 > --- a/arch/x86/include/asm/perf_event.h > +++ b/arch/x86/include/asm/perf_event.h > @@ -492,9 +492,11 @@ static inline void perf_check_microcode(void) { } > > #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) > extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); > +extern u64 perf_get_hw_event_config(int perf_hw_id); > extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr); > #else > struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); > +u64 perf_get_hw_event_config(int perf_hw_id); Should this be an inline that returns 0? > static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) > { > return -1; Peter, please review/ack this. Paolo