From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964794AbcBCRMV (ORCPT ); Wed, 3 Feb 2016 12:12:21 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:34919 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752217AbcBCRMT (ORCPT ); Wed, 3 Feb 2016 12:12:19 -0500 From: Jan Glauber To: Will Deacon , Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jan Glauber Subject: [PATCH v3 0/5] Cavium ThunderX PMU support Date: Wed, 3 Feb 2016 18:11:55 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, I'm reposting the whole series just in case my previous attempt to repost only the broken patch was confusing. Patches are based on 4.5-rc2. Patches 1-3 add support for ThunderX specific PMU events. Patch 4 changes the cycle counter to overflow on 64 bit but tries to minimize code changes. Without this change perf does not work at all on ThunderX. Patch 5 extends the event mask according to ARMv8.1 and also affects arm32. Changes to v2: - fixed arm compile errors Changes to v1: - renamed thunderx dt pmu binding to thunder --Jan Jan Glauber (5): arm64/perf: Rename Cortex A57 events arm64/perf: Add Cavium ThunderX PMU support arm64: dts: Add Cavium ThunderX specific PMU arm64/perf: Enable PMCR long cycle counter bit arm64/perf: Extend event mask for ARMv8.1 Documentation/devicetree/bindings/arm/pmu.txt | 1 + arch/arm/kernel/perf_event_v6.c | 6 +- arch/arm/kernel/perf_event_v7.c | 29 ++++-- arch/arm/kernel/perf_event_xscale.c | 4 +- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 5 + arch/arm64/kernel/perf_event.c | 145 ++++++++++++++++++++------ drivers/perf/arm_pmu.c | 5 +- include/linux/perf/arm_pmu.h | 4 +- 8 files changed, 151 insertions(+), 48 deletions(-) -- 1.9.1