[PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf

[Reinette Chatre <reinette.chatre@intel.com>]

Dear Maintainers,

The success of Cache Pseudo-Locking can be measured via the use of
performance events. Specifically, the number of cache hits and misses
reading a memory region after it has been pseudo-locked to cache. This
measurement is triggered via the resctrl debugfs interface.

To ensure most accurate results the performance counters and their
configuration registers are accessed directly. This is currently done
without coordination with other performance event users and will have
consequences any time two users, for example perf and cache
pseudo-locking, attempt to do any kind of measurement at the same time.

The performance counter reservation mechanism for individual counters is
available to cache pseudo-locking and could be used. That would require
duplicating the currently private reservation mechanism for all counters.
Instead in this work the reservation mechanism for all counters on the
system is exposed and subsequently used by the cache pseudo-locking
measurement code.

Your feedback on this work will be greatly appreciated.

Reinette

Reinette Chatre (2):
  perf/x86: Expose PMC hardware reservation
  x86/intel_rdt: Coordinate performance monitoring with perf

 Documentation/x86/intel_rdt_ui.txt          | 4 ----
 arch/x86/events/core.c                      | 6 ++++--
 arch/x86/kernel/cpu/intel_rdt.h             | 2 ++
 arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c | 8 ++++++++
 4 files changed, 14 insertions(+), 6 deletions(-)

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2.17.0