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From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
To: "Marc Zyngier" <maz@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Andreas Färber" <afaerber@suse.de>
Cc: parthiban@linumiz.com, Saravanan Sekar <sravanhome@gmail.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-actions@lists.infradead.org
Subject: [PATCH v7 0/3] Add Actions Semi Owl family sirq support
Date: Mon, 14 Sep 2020 23:27:16 +0300	[thread overview]
Message-ID: <cover.1600114378.git.cristian.ciocaltea@gmail.com> (raw)

This patch series adds support for the external interrupt controller
(SIRQ) found in the Actions Semi Owl family of SoC's (S500, S700 and
S900). The controller handles up to 3 external interrupt lines through
dedicated SIRQ pins.

This is a rework of the patch series submitted some time ago by 
Parthiban Nallathambi: 
https://lore.kernel.org/lkml/20181126100356.2840578-1-pn@denx.de/

Please note I have dropped, for the moment, the S700 related patches 
since I do not own a compatible hardware for testing. I'm using instead
an S500 SoC based board for which I have already provided the initial
support:
https://lore.kernel.org/lkml/cover.1598621459.git.cristian.ciocaltea@gmail.com/

Additionally, I have taken the authorship for the driver patch,
considering the original code has been already modified to a great
extent and I'm firmly committed to maintaining it in the long run.

The SIRQ controller support is a prerequisite of the upcoming MFD
driver for the Actions Semi ATC260x PMICs.

Thanks and regards,
Cristi

Changes in v7:
- Added Co-developed-by tags to the driver patch according to Marc's
  review

Changes in v6:
- Integrated binding doc related feedback from Rob and Marc
- Updated cover letter to handle the authorship issue indicated by Mani
- Rebased patch series on v5.9-rc4

Changes in v5:
- Integrated Marc's review (more details in the driver patch changelog)
- Rebased patch series on v5.9-rc1

Changes in v4:
- Simplified the DTS structure:
  * dropped 'actions,sirq-shared-reg' node, now the differentiation
    between SoC variants is handled via the compatible property
  * dropped 'actions,sirq-reg-offset', now controller base address in
    DTS points to SIRQ0 register, so no additional information is
    required for S500 and S700, while for S900 SoC the offsets of SIRQ1
    and SIRQ2 regs are provided by the driver
  * 'actions,ext-irq-range' was replaced with 'actions,ext-interrupts',
    an array of the GIC interrupts triggered by the controller
- Fixed wrong INTC_EXTCTL_TYPE_MASK definition
- Removed redundant irq_fwspec checks in owl_sirq_domain_alloc()
- Improved error handling in owl_sirq_of_init()
- Added yaml binding document
- Dropped S700 related DTS patches for lack of testing hardware:
  * arm64: dts: actions: Add sirq node for Actions Semi S700
  * arm64: dts: actions: s700-cubieboard7: Enable SIRQ
- Updated MAINTAINERS
- Rebased patchset on kernel v5.8
- Cosmetic changes
 * Ordered include statements alphabetically
 * Added comment to owl_sirq_set_type() describing conversion of falling
   edge or active low signals
 * Replaced IRQF_TRIGGER_* with corresponding IRQ_TYPE_* variants
 * Ensured data types and function naming are consistent regarding the
   'owl_sirq' prefix

Changes in v3 (Parthiban Nallathambi):
- Set default operating frequency to 24MHz
- Falling edge and Low Level interrupts translated to rising edge and high level
- Introduced common function with lock handling for register read and write
- Used direct GIC interrupt number for interrupt local hwirq and finding offset
using DT entry (range) when registers are shared 
- Changed irq_ack to irq_eoi
- Added translation method for irq_domain_ops
- Clearing interrupt pending based on bitmask for edge triggered
- Added pinctrl definition for sirq for cubieboard7. This depends on,
https://lore.kernel.org/patchwork/patch/1012859/

Changes in v2 (Parthiban Nallathambi):
- Added SIRQ as hierarchical chip
        GIC <----> SIRQ <----> External interrupt controller/Child devices
- Device binding updates with vendor prefix
- Register sharing handled globally and common init sequence/data for all
actions SoC family

Cristian Ciocaltea (3):
  dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
  irqchip: Add Actions Semi Owl SIRQ controller
  MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller

 .../actions,owl-sirq.yaml                     |  65 ++++
 MAINTAINERS                                   |   2 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-owl-sirq.c                | 359 ++++++++++++++++++
 4 files changed, 427 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
 create mode 100644 drivers/irqchip/irq-owl-sirq.c

-- 
2.28.0


             reply	other threads:[~2020-09-14 20:29 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-14 20:27 Cristian Ciocaltea [this message]
2020-09-14 20:27 ` [PATCH v7 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding Cristian Ciocaltea
2020-09-22 23:42   ` Rob Herring
2020-09-23  7:24     ` Cristian Ciocaltea
2020-09-14 20:27 ` [PATCH v7 2/3] irqchip: Add Actions Semi Owl SIRQ controller Cristian Ciocaltea
2020-09-14 20:27 ` [PATCH v7 3/3] MAINTAINERS: Add entries for " Cristian Ciocaltea
2020-09-25 16:00 ` [PATCH v7 0/3] Add Actions Semi Owl family sirq support Marc Zyngier

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