[PATCH v2 00/18] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

[PATCH v2 00/18] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

[Cristian Ciocaltea]

Hi,

This patchset brings a series of improvements for the Actions Semi S500
SoCs family, by adding support for Clock & Reset Management Units, DMA,
MMC, I2C & SIRQ controllers.

Please note the patches consist mostly of DTS and bindings/compatibles
changes, since all the work they depend on has been already merged,
i.e. clock fixes/additions, pinctrl driver, sirq driver.

For the moment, I have only enabled the features I could test on
RoseapplePi SBC.

Thanks,
Cristi

Changes in v2:
- Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
- Added support for the SIRQ controller
- Added new entries in MAINTAINERS
- Updated naming of some patches in v1

Cristian Ciocaltea (18):
  arm: dts: owl-s500: Add Clock Management Unit
  arm: dts: owl-s500: Set CMU clocks for UARTs
  arm: dts: owl-s500: Add Reset controller
  dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
  dmaengine: owl: Add compatible for the Actions Semi S500 DMA
    controller
  arm: dts: owl-s500: Add DMA controller
  arm: dts: owl-s500: Add pinctrl & GPIO support
  dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
  arm: dts: owl-s500: Add MMC support
  dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
  MAINTAINERS: Update entry for Actions Semi Owl I2C binding
  i2c: owl: Add compatible for the Actions Semi S500 I2C controller
  arm: dts: owl-s500: Add I2C support
  arm: dts: owl-s500: Add SIRQ controller
  arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
  arm: dts: owl-s500-roseapplepi: Add uSD support
  arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
  MAINTAINERS: Add linux-actions ML for Actions Semi Arch

 .../devicetree/bindings/dma/owl-dma.yaml      |   5 +-
 .../devicetree/bindings/i2c/i2c-owl.txt       |  29 ----
 .../devicetree/bindings/i2c/i2c-owl.yaml      |  62 ++++++++
 .../devicetree/bindings/mmc/owl-mmc.yaml      |   4 +-
 MAINTAINERS                                   |   3 +-
 arch/arm/boot/dts/owl-s500-roseapplepi.dts    |  97 +++++++++++-
 arch/arm/boot/dts/owl-s500.dtsi               | 140 ++++++++++++++++++
 drivers/dma/owl-dma.c                         |   1 +
 drivers/i2c/busses/i2c-owl.c                  |   1 +
 9 files changed, 304 insertions(+), 38 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml

-- 
2.29.2

[PATCH v2 01/18] arm: dts: owl-s500: Add Clock Management Unit

[Cristian Ciocaltea]

Add Clock Management Unit for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 1dbe4e8b38ac..5d5ad9db549b 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2016-2017 Andreas Färber
  */
 
+#include <dt-bindings/clock/actions,s500-cmu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/owl-s500-powergate.h>
 
@@ -70,6 +71,12 @@ hosc: hosc {
 		#clock-cells = <0>;
 	};
 
+	losc: losc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -169,6 +176,13 @@ uart6: serial@b012c000 {
 			status = "disabled";
 		};
 
+		cmu: clock-controller@b0160000 {
+			compatible = "actions,s500-cmu";
+			reg = <0xb0160000 0x8000>;
+			clocks = <&hosc>, <&losc>;
+			#clock-cells = <1>;
+		};
+
 		timer: timer@b0168000 {
 			compatible = "actions,s500-timer";
 			reg = <0xb0168000 0x8000>;
-- 
2.29.2

[PATCH v2 02/18] arm: dts: owl-s500: Set CMU clocks for UARTs

[Cristian Ciocaltea]

Set Clock Management Unit clocks for the UART nodes of Actions Semi
S500 SoCs.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 5d5ad9db549b..ac3d04c75dd5 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -131,6 +131,7 @@ uart0: serial@b0120000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb0120000 0x2000>;
 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART0>;
 			status = "disabled";
 		};
 
@@ -138,6 +139,7 @@ uart1: serial@b0122000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb0122000 0x2000>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART1>;
 			status = "disabled";
 		};
 
@@ -145,6 +147,7 @@ uart2: serial@b0124000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb0124000 0x2000>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART2>;
 			status = "disabled";
 		};
 
@@ -152,6 +155,7 @@ uart3: serial@b0126000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb0126000 0x2000>;
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART3>;
 			status = "disabled";
 		};
 
@@ -159,6 +163,7 @@ uart4: serial@b0128000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb0128000 0x2000>;
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART4>;
 			status = "disabled";
 		};
 
@@ -166,6 +171,7 @@ uart5: serial@b012a000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb012a000 0x2000>;
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART5>;
 			status = "disabled";
 		};
 
@@ -173,6 +179,7 @@ uart6: serial@b012c000 {
 			compatible = "actions,s500-uart", "actions,owl-uart";
 			reg = <0xb012c000 0x2000>;
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_UART6>;
 			status = "disabled";
 		};
 
-- 
2.29.2

[PATCH v2 03/18] arm: dts: owl-s500: Add Reset controller

[Cristian Ciocaltea]

Add reset controller property and bindings header for the
Actions Semi S500 SoC DTS.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index ac3d04c75dd5..a57ce7d6d745 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/actions,s500-cmu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/owl-s500-powergate.h>
+#include <dt-bindings/reset/actions,s500-reset.h>
 
 / {
 	compatible = "actions,s500";
@@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 {
 			reg = <0xb0160000 0x8000>;
 			clocks = <&hosc>, <&losc>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		timer: timer@b0168000 {
-- 
2.29.2

[PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Cristian Ciocaltea]

Add a new compatible string corresponding to the DMA controller found
in the S500 variant of the Actions Semi Owl SoCs family.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
index 256d62af2c64..f085f0e42d2c 100644
--- a/Documentation/devicetree/bindings/dma/owl-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
@@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller
 
 description: |
   The OWL DMA is a general-purpose direct memory access controller capable of
-  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
-  respectively.
+  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
+  independent DMA channels for the S500 and S900 SoC variants.
 
 maintainers:
   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@@ -22,6 +22,7 @@ properties:
     enum:
       - actions,s900-dma
       - actions,s700-dma
+      - actions,s500-dma
 
   reg:
     maxItems: 1
-- 
2.29.2

[PATCH v2 05/18] dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller

[Cristian Ciocaltea]

The DMA controller present on the Actions Semi S500 SoC is compatible
with the S900 variant, so add it to the list of devices supported by
the Actions Semi Owl DMA driver.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 drivers/dma/owl-dma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
index 9fede32641e9..54e509de66e2 100644
--- a/drivers/dma/owl-dma.c
+++ b/drivers/dma/owl-dma.c
@@ -1082,6 +1082,7 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
 static const struct of_device_id owl_dma_match[] = {
 	{ .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
 	{ .compatible = "actions,s700-dma", .data = (void *)S700_DMA,},
+	{ .compatible = "actions,s500-dma", .data = (void *)S900_DMA,},
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, owl_dma_match);
-- 
2.29.2

[PATCH v2 06/18] arm: dts: owl-s500: Add DMA controller

[Cristian Ciocaltea]

Add DMA controller node for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index a57ce7d6d745..449e9807c4ec 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -207,5 +207,19 @@ sps: power-controller@b01b0100 {
 			reg = <0xb01b0100 0x100>;
 			#power-domain-cells = <1>;
 		};
+
+		dma: dma-controller@b0260000 {
+			compatible = "actions,s500-dma";
+			reg = <0xb0260000 0xd00>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			dma-channels = <12>;
+			dma-requests = <46>;
+			clocks = <&cmu CLK_DMAC>;
+			power-domains = <&sps S500_PD_DMA>;
+		};
 	};
 };
-- 
2.29.2

[PATCH v2 07/18] arm: dts: owl-s500: Add pinctrl & GPIO support

[Cristian Ciocaltea]

Add pinctrl node for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 449e9807c4ec..b16172615db0 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/clock/actions,s500-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/owl-s500-powergate.h>
 #include <dt-bindings/reset/actions,s500-reset.h>
@@ -208,6 +209,25 @@ sps: power-controller@b01b0100 {
 			#power-domain-cells = <1>;
 		};
 
+		pinctrl: pinctrl@b01b0000 {
+			compatible = "actions,s500-pinctrl";
+			reg = <0xb01b0000 0x40>, /* GPIO */
+			      <0xb01b0040 0x10>, /* Multiplexing Control */
+			      <0xb01b0060 0x18>, /* PAD Control */
+			      <0xb01b0080 0xc>;  /* PAD Drive Capacity */
+			clocks = <&cmu CLK_GPIO>;
+			gpio-controller;
+			gpio-ranges = <&pinctrl 0 0 132>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
+				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
+		};
+
 		dma: dma-controller@b0260000 {
 			compatible = "actions,s500-dma";
 			reg = <0xb0260000 0xd00>;
-- 
2.29.2

[PATCH v2 08/18] dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC

[Cristian Ciocaltea]

Add a new compatible string corresponding to the MMC controller found
in the S500 variant of the Actions Semi Owl SoCs family.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 Documentation/devicetree/bindings/mmc/owl-mmc.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
index b6ab527087d5..b0d81ebe0f6e 100644
--- a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
@@ -17,7 +17,9 @@ properties:
     oneOf:
       - const: actions,owl-mmc
       - items:
-          - const: actions,s700-mmc
+          - enum:
+              - actions,s500-mmc
+              - actions,s700-mmc
           - const: actions,owl-mmc
 
   reg:
-- 
2.29.2

[PATCH v2 09/18] arm: dts: owl-s500: Add MMC support

[Cristian Ciocaltea]

Add MMC controller nodes for Actions Semi S500 SoC, in order to
facilitate access to SD/EMMC/SDIO cards.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index b16172615db0..7af7c9e1119d 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -241,5 +241,38 @@ dma: dma-controller@b0260000 {
 			clocks = <&cmu CLK_DMAC>;
 			power-domains = <&sps S500_PD_DMA>;
 		};
+
+		mmc0: mmc@b0230000 {
+			compatible = "actions,s500-mmc", "actions,owl-mmc";
+			reg = <0xb0230000 0x38>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD0>;
+			resets = <&cmu RESET_SD0>;
+			dmas = <&dma 2>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
+
+		mmc1: mmc@b0234000 {
+			compatible = "actions,s500-mmc", "actions,owl-mmc";
+			reg = <0xb0234000 0x38>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD1>;
+			resets = <&cmu RESET_SD1>;
+			dmas = <&dma 3>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
+
+		mmc2: mmc@b0238000 {
+			compatible = "actions,s500-mmc", "actions,owl-mmc";
+			reg = <0xb0238000 0x38>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD2>;
+			resets = <&cmu RESET_SD2>;
+			dmas = <&dma 4>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
 	};
 };
-- 
2.29.2

[PATCH v2 10/18] dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema

[Cristian Ciocaltea]

Convert the Actions Semi Owl I2C DT binding to a YAML schema for
enabling DT validation.

Additionally, add a new compatible string corresponding to the I2C
controller found in the S500 variant of the Actions Semi Owl SoCs
family.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 .../devicetree/bindings/i2c/i2c-owl.txt       | 29 ---------
 .../devicetree/bindings/i2c/i2c-owl.yaml      | 62 +++++++++++++++++++
 2 files changed, 62 insertions(+), 29 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml

diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt
deleted file mode 100644
index 54c05dbdb2e4..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-owl.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Actions Semiconductor Owl I2C controller
-
-Required properties:
-
-- compatible        : Should be one of the following:
-		      - "actions,s700-i2c" for S700 SoC
-		      - "actions,s900-i2c" for S900 SoC
-- reg               : Offset and length of the register set for the device.
-- #address-cells    : Should be 1.
-- #size-cells       : Should be 0.
-- interrupts        : A single interrupt specifier.
-- clocks            : Phandle of the clock feeding the I2C controller.
-
-Optional properties:
-
-- clock-frequency   : Desired I2C bus clock frequency in Hz. As only Normal and
-                      Fast modes are supported, possible values are 100000 and
-                      400000.
-Examples:
-
-        i2c0: i2c@e0170000 {
-                compatible = "actions,s900-i2c";
-                reg = <0 0xe0170000 0 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C0>;
-                clock-frequency = <100000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.yaml b/Documentation/devicetree/bindings/i2c/i2c-owl.yaml
new file mode 100644
index 000000000000..d96908badf81
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-owl.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-owl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl I2C Controller
+
+maintainers:
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+  This I2C controller is found in the Actions Semi Owl SoCs:
+  S500, S700 and S900.
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - actions,s500-i2c # Actions Semi S500 compatible SoCs
+      - actions,s700-i2c # Actions Semi S700 compatible SoCs
+      - actions,s900-i2c # Actions Semi S900 compatible SoCs
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: Phandle of the clock feeding the I2C controller.
+    minItems: 1
+
+  clock-frequency:
+    description: |
+      Desired I2C bus clock frequency in Hz. As only Standard and Fast
+      modes are supported, possible values are 100000 and 400000.
+    enum: [100000, 400000]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/actions,s900-cmu.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    i2c@e0170000 {
+        compatible = "actions,s900-i2c";
+        reg = <0xe0170000 0x1000>;
+        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cmu CLK_I2C0>;
+        clock-frequency = <100000>;
+    };
+
+...
-- 
2.29.2

[PATCH v2 11/18] MAINTAINERS: Update entry for Actions Semi Owl I2C binding

[Cristian Ciocaltea]

The Actions Semi Owl I2C DT binding has been converted to YAML schema,
therefore update accordingly the entry in MAINTAINERS.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index e451dcce054f..a85c1881cf07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1501,7 +1501,7 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/arm/actions.yaml
 F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
 F:	Documentation/devicetree/bindings/dma/owl-dma.yaml
-F:	Documentation/devicetree/bindings/i2c/i2c-owl.txt
+F:	Documentation/devicetree/bindings/i2c/i2c-owl.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
 F:	Documentation/devicetree/bindings/mmc/owl-mmc.yaml
 F:	Documentation/devicetree/bindings/pinctrl/actions,*
-- 
2.29.2

[PATCH v2 12/18] i2c: owl: Add compatible for the Actions Semi S500 I2C controller

[Cristian Ciocaltea]

Add S500 variant to the list of devices supported by the Actions Semi
Owl I2C driver.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 drivers/i2c/busses/i2c-owl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
index 5cf5a119a6ad..98882fe4e965 100644
--- a/drivers/i2c/busses/i2c-owl.c
+++ b/drivers/i2c/busses/i2c-owl.c
@@ -508,6 +508,7 @@ static int owl_i2c_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id owl_i2c_of_match[] = {
+	{ .compatible = "actions,s500-i2c" },
 	{ .compatible = "actions,s700-i2c" },
 	{ .compatible = "actions,s900-i2c" },
 	{ /* sentinel */ }
-- 
2.29.2

[PATCH v2 13/18] arm: dts: owl-s500: Add I2C support

[Cristian Ciocaltea]

Add I2C controller nodes for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 7af7c9e1119d..55f8b8c2e149 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 {
 			#reset-cells = <1>;
 		};
 
+		i2c0: i2c@b0170000 {
+			compatible = "actions,s500-i2c";
+			reg = <0xb0170000 0x4000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@b0174000 {
+			compatible = "actions,s500-i2c";
+			reg = <0xb0174000 0x4000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@b0178000 {
+			compatible = "actions,s500-i2c";
+			reg = <0xb0178000 0x4000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@b017c000 {
+			compatible = "actions,s500-i2c";
+			reg = <0xb017c000 0x4000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		timer: timer@b0168000 {
 			compatible = "actions,s500-timer";
 			reg = <0xb0168000 0x8000>;
-- 
2.29.2

[PATCH v2 14/18] arm: dts: owl-s500: Add SIRQ controller

[Cristian Ciocaltea]

Add SIRQ controller node for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 55f8b8c2e149..cd635f222d26 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -233,6 +233,16 @@ i2c3: i2c@b017c000 {
 			status = "disabled";
 		};
 
+		sirq: interrupt-controller@b01b0200 {
+			compatible = "actions,s500-sirq";
+			reg = <0xb01b0200 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
+		};
+
 		timer: timer@b0168000 {
 			compatible = "actions,s500-timer";
 			reg = <0xb0168000 0x8000>;
-- 
2.29.2

[PATCH v2 15/18] arm: dts: owl-s500-roseapplepi: Use UART clock from CMU

[Cristian Ciocaltea]

Remove the UART fixed clock for RoseapplePi SBC and switch to using
the clock provided by CMU.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index a2087e617cb2..800edf5d2d12 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -25,12 +25,6 @@ memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x80000000>; /* 2GB */
 	};
-
-	uart2_clk: uart2-clk {
-		compatible = "fixed-clock";
-		clock-frequency = <921600>;
-		#clock-cells = <0>;
-	};
 };
 
 &twd_timer {
@@ -43,5 +37,4 @@ &timer {
 
 &uart2 {
 	status = "okay";
-	clocks = <&uart2_clk>;
 };
-- 
2.29.2

[PATCH v2 16/18] arm: dts: owl-s500-roseapplepi: Add uSD support

[Cristian Ciocaltea]

Add uSD support for RoseapplePi SBC using a fixed regulator as a
temporary solution until PMIC support becomes available.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index 800edf5d2d12..fe9ae3619422 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -14,6 +14,7 @@ / {
 	model = "Roseapple Pi";
 
 	aliases {
+		mmc0 = &mmc0;
 		serial2 = &uart2;
 	};
 
@@ -25,6 +26,55 @@ memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x80000000>; /* 2GB */
 	};
+
+	/* Fixed regulator used in the absence of PMIC */
+	sd_vcc: sd-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.1V";
+		regulator-min-microvolt = <3100000>;
+		regulator-max-microvolt = <3100000>;
+		regulator-always-on;
+	};
+};
+
+&pinctrl {
+	mmc0_pins: mmc0-pins {
+		pinmux {
+			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
+				 "sd0_cmd_mfp", "sd0_clk_mfp";
+			function = "sd0";
+		};
+
+		drv-pinconf {
+			groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
+			drive-strength = <8>;
+		};
+
+		bias0-pinconf {
+			pins = "sd0_d0", "sd0_d1", "sd0_d2",
+			       "sd0_d3", "sd0_cmd";
+			bias-pull-up;
+		};
+
+		bias1-pinconf {
+			pins = "sd0_clk";
+			bias-pull-down;
+		};
+	};
+};
+
+/* uSD */
+&mmc0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	no-sdio;
+	no-mmc;
+	no-1-8-v;
+	cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&sd_vcc>;
+	vqmmc-supply = <&sd_vcc>;
 };
 
 &twd_timer {
-- 
2.29.2

[PATCH v2 17/18] arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration

[Cristian Ciocaltea]

Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC.
For the moment enable only I2C0, which is used by the ATC2603C PMIC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index fe9ae3619422..ff91561ca99c 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -37,7 +37,51 @@ sd_vcc: sd-vcc {
 	};
 };
 
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+};
+
 &pinctrl {
+	i2c0_pins: i2c0-pins {
+		pinmux {
+			groups = "i2c0_mfp";
+			function = "i2c0";
+		};
+
+		pinconf {
+			pins = "i2c0_sclk", "i2c0_sdata";
+			bias-pull-up;
+		};
+	};
+
+	i2c1_pins: i2c1-pins {
+		pinconf {
+			pins = "i2c1_sclk", "i2c1_sdata";
+			bias-pull-up;
+		};
+	};
+
+	i2c2_pins: i2c2-pins {
+		pinconf {
+			pins = "i2c2_sclk", "i2c2_sdata";
+			bias-pull-up;
+		};
+	};
+
 	mmc0_pins: mmc0-pins {
 		pinmux {
 			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
-- 
2.29.2

[PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Cristian Ciocaltea]

Add the linux-actions mailing list for the Actions Semi architecture.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a85c1881cf07..8428aba52581 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
 M:	Andreas Färber <afaerber@suse.de>
 M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/actions.yaml
 F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
-- 
2.29.2

Re: [PATCH v2 08/18] dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC

[Ulf Hansson]

On Fri, 20 Nov 2020 at 00:56, Cristian Ciocaltea
<cristian.ciocaltea@gmail.com> wrote:
>
> Add a new compatible string corresponding to the MMC controller found
> in the S500 variant of the Actions Semi Owl SoCs family.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  Documentation/devicetree/bindings/mmc/owl-mmc.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> index b6ab527087d5..b0d81ebe0f6e 100644
> --- a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> @@ -17,7 +17,9 @@ properties:
>      oneOf:
>        - const: actions,owl-mmc
>        - items:
> -          - const: actions,s700-mmc
> +          - enum:
> +              - actions,s500-mmc
> +              - actions,s700-mmc
>            - const: actions,owl-mmc
>
>    reg:
> --
> 2.29.2
>

Re: [PATCH v2 09/18] arm: dts: owl-s500: Add MMC support

[Ulf Hansson]

On Fri, 20 Nov 2020 at 00:56, Cristian Ciocaltea
<cristian.ciocaltea@gmail.com> wrote:
>
> Add MMC controller nodes for Actions Semi S500 SoC, in order to
> facilitate access to SD/EMMC/SDIO cards.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>

Kind regards
Uffe


> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index b16172615db0..7af7c9e1119d 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 {
>                         clocks = <&cmu CLK_DMAC>;
>                         power-domains = <&sps S500_PD_DMA>;
>                 };
> +
> +               mmc0: mmc@b0230000 {
> +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> +                       reg = <0xb0230000 0x38>;
> +                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cmu CLK_SD0>;
> +                       resets = <&cmu RESET_SD0>;
> +                       dmas = <&dma 2>;
> +                       dma-names = "mmc";
> +                       status = "disabled";
> +               };
> +
> +               mmc1: mmc@b0234000 {
> +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> +                       reg = <0xb0234000 0x38>;
> +                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cmu CLK_SD1>;
> +                       resets = <&cmu RESET_SD1>;
> +                       dmas = <&dma 3>;
> +                       dma-names = "mmc";
> +                       status = "disabled";
> +               };
> +
> +               mmc2: mmc@b0238000 {
> +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> +                       reg = <0xb0238000 0x38>;
> +                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cmu CLK_SD2>;
> +                       resets = <&cmu RESET_SD2>;
> +                       dmas = <&dma 4>;
> +                       dma-names = "mmc";
> +                       status = "disabled";
> +               };
>         };
>  };
> --
> 2.29.2
>

Re: [PATCH v2 09/18] arm: dts: owl-s500: Add MMC support

[Cristian Ciocaltea]

On Tue, Nov 24, 2020 at 03:25:15PM +0100, Ulf Hansson wrote:
> On Fri, 20 Nov 2020 at 00:56, Cristian Ciocaltea
> <cristian.ciocaltea@gmail.com> wrote:
> >
> > Add MMC controller nodes for Actions Semi S500 SoC, in order to
> > facilitate access to SD/EMMC/SDIO cards.
> >
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> 
> Kind regards
> Uffe
> 

Thanks for the review!

Regards,
Cristi

> 
> > ---
> >  arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> > index b16172615db0..7af7c9e1119d 100644
> > --- a/arch/arm/boot/dts/owl-s500.dtsi
> > +++ b/arch/arm/boot/dts/owl-s500.dtsi
> > @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 {
> >                         clocks = <&cmu CLK_DMAC>;
> >                         power-domains = <&sps S500_PD_DMA>;
> >                 };
> > +
> > +               mmc0: mmc@b0230000 {
> > +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> > +                       reg = <0xb0230000 0x38>;
> > +                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cmu CLK_SD0>;
> > +                       resets = <&cmu RESET_SD0>;
> > +                       dmas = <&dma 2>;
> > +                       dma-names = "mmc";
> > +                       status = "disabled";
> > +               };
> > +
> > +               mmc1: mmc@b0234000 {
> > +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> > +                       reg = <0xb0234000 0x38>;
> > +                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cmu CLK_SD1>;
> > +                       resets = <&cmu RESET_SD1>;
> > +                       dmas = <&dma 3>;
> > +                       dma-names = "mmc";
> > +                       status = "disabled";
> > +               };
> > +
> > +               mmc2: mmc@b0238000 {
> > +                       compatible = "actions,s500-mmc", "actions,owl-mmc";
> > +                       reg = <0xb0238000 0x38>;
> > +                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cmu CLK_SD2>;
> > +                       resets = <&cmu RESET_SD2>;
> > +                       dmas = <&dma 4>;
> > +                       dma-names = "mmc";
> > +                       status = "disabled";
> > +               };
> >         };
> >  };
> > --
> > 2.29.2
> >

Re: [PATCH v2 12/18] i2c: owl: Add compatible for the Actions Semi S500 I2C controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:06AM +0200, Cristian Ciocaltea wrote:
> Add S500 variant to the list of devices supported by the Actions Semi
> Owl I2C driver.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Ah, I thought S500 support needs some change...

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/i2c/busses/i2c-owl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> index 5cf5a119a6ad..98882fe4e965 100644
> --- a/drivers/i2c/busses/i2c-owl.c
> +++ b/drivers/i2c/busses/i2c-owl.c
> @@ -508,6 +508,7 @@ static int owl_i2c_probe(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id owl_i2c_of_match[] = {
> +	{ .compatible = "actions,s500-i2c" },
>  	{ .compatible = "actions,s700-i2c" },
>  	{ .compatible = "actions,s900-i2c" },
>  	{ /* sentinel */ }
> -- 
> 2.29.2
> 

Re: [PATCH v2 01/18] arm: dts: owl-s500: Add Clock Management Unit

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:55AM +0200, Cristian Ciocaltea wrote:
> Add Clock Management Unit for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 1dbe4e8b38ac..5d5ad9db549b 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -5,6 +5,7 @@
>   * Copyright (c) 2016-2017 Andreas Färber
>   */
>  
> +#include <dt-bindings/clock/actions,s500-cmu.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/owl-s500-powergate.h>
>  
> @@ -70,6 +71,12 @@ hosc: hosc {
>  		#clock-cells = <0>;
>  	};
>  
> +	losc: losc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		#clock-cells = <0>;
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <1>;
> @@ -169,6 +176,13 @@ uart6: serial@b012c000 {
>  			status = "disabled";
>  		};
>  
> +		cmu: clock-controller@b0160000 {
> +			compatible = "actions,s500-cmu";
> +			reg = <0xb0160000 0x8000>;
> +			clocks = <&hosc>, <&losc>;
> +			#clock-cells = <1>;
> +		};
> +
>  		timer: timer@b0168000 {
>  			compatible = "actions,s500-timer";
>  			reg = <0xb0168000 0x8000>;
> -- 
> 2.29.2
> 

Re: [PATCH v2 02/18] arm: dts: owl-s500: Set CMU clocks for UARTs

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:56AM +0200, Cristian Ciocaltea wrote:
> Set Clock Management Unit clocks for the UART nodes of Actions Semi
> S500 SoCs.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Also in this patch itself, you need to remove the dummy "uart3_clk" from
S500 dts. With that,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 5d5ad9db549b..ac3d04c75dd5 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -131,6 +131,7 @@ uart0: serial@b0120000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb0120000 0x2000>;
>  			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART0>;
>  			status = "disabled";
>  		};
>  
> @@ -138,6 +139,7 @@ uart1: serial@b0122000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb0122000 0x2000>;
>  			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART1>;
>  			status = "disabled";
>  		};
>  
> @@ -145,6 +147,7 @@ uart2: serial@b0124000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb0124000 0x2000>;
>  			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART2>;
>  			status = "disabled";
>  		};
>  
> @@ -152,6 +155,7 @@ uart3: serial@b0126000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb0126000 0x2000>;
>  			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART3>;
>  			status = "disabled";
>  		};
>  
> @@ -159,6 +163,7 @@ uart4: serial@b0128000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb0128000 0x2000>;
>  			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART4>;
>  			status = "disabled";
>  		};
>  
> @@ -166,6 +171,7 @@ uart5: serial@b012a000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb012a000 0x2000>;
>  			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART5>;
>  			status = "disabled";
>  		};
>  
> @@ -173,6 +179,7 @@ uart6: serial@b012c000 {
>  			compatible = "actions,s500-uart", "actions,owl-uart";
>  			reg = <0xb012c000 0x2000>;
>  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART6>;
>  			status = "disabled";
>  		};
>  
> -- 
> 2.29.2
> 

Re: [PATCH v2 03/18] arm: dts: owl-s500: Add Reset controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:57AM +0200, Cristian Ciocaltea wrote:
> Add reset controller property and bindings header for the
> Actions Semi S500 SoC DTS.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index ac3d04c75dd5..a57ce7d6d745 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/clock/actions,s500-cmu.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/owl-s500-powergate.h>
> +#include <dt-bindings/reset/actions,s500-reset.h>
>  
>  / {
>  	compatible = "actions,s500";
> @@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 {
>  			reg = <0xb0160000 0x8000>;
>  			clocks = <&hosc>, <&losc>;
>  			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  
>  		timer: timer@b0168000 {
> -- 
> 2.29.2
> 

Re: [PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:58AM +0200, Cristian Ciocaltea wrote:
> Add a new compatible string corresponding to the DMA controller found
> in the S500 variant of the Actions Semi Owl SoCs family.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> index 256d62af2c64..f085f0e42d2c 100644
> --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> @@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller
>  
>  description: |
>    The OWL DMA is a general-purpose direct memory access controller capable of
> -  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
> -  respectively.
> +  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
> +  independent DMA channels for the S500 and S900 SoC variants.
>  
>  maintainers:
>    - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> @@ -22,6 +22,7 @@ properties:
>      enum:
>        - actions,s900-dma
>        - actions,s700-dma
> +      - actions,s500-dma
>  
>    reg:
>      maxItems: 1
> -- 
> 2.29.2
> 

Re: [PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:58AM +0200, Cristian Ciocaltea wrote:
> Add a new compatible string corresponding to the DMA controller found
> in the S500 variant of the Actions Semi Owl SoCs family.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> index 256d62af2c64..f085f0e42d2c 100644
> --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> @@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller
>  
>  description: |
>    The OWL DMA is a general-purpose direct memory access controller capable of
> -  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
> -  respectively.
> +  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
> +  independent DMA channels for the S500 and S900 SoC variants.
>  
>  maintainers:
>    - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> @@ -22,6 +22,7 @@ properties:
>      enum:
>        - actions,s900-dma
>        - actions,s700-dma
> +      - actions,s500-dma

I think we should order the entries now...

>  
>    reg:
>      maxItems: 1
> -- 
> 2.29.2
> 

Re: [PATCH v2 05/18] dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:55:59AM +0200, Cristian Ciocaltea wrote:
> The DMA controller present on the Actions Semi S500 SoC is compatible
> with the S900 variant, so add it to the list of devices supported by
> the Actions Semi Owl DMA driver.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

I hope that you have verified both Memcpy and Slave transfers...

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/dma/owl-dma.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
> index 9fede32641e9..54e509de66e2 100644
> --- a/drivers/dma/owl-dma.c
> +++ b/drivers/dma/owl-dma.c
> @@ -1082,6 +1082,7 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
>  static const struct of_device_id owl_dma_match[] = {
>  	{ .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
>  	{ .compatible = "actions,s700-dma", .data = (void *)S700_DMA,},
> +	{ .compatible = "actions,s500-dma", .data = (void *)S900_DMA,},
>  	{ /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, owl_dma_match);
> -- 
> 2.29.2
> 

Re: [PATCH v2 06/18] arm: dts: owl-s500: Add DMA controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:00AM +0200, Cristian Ciocaltea wrote:
> Add DMA controller node for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index a57ce7d6d745..449e9807c4ec 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -207,5 +207,19 @@ sps: power-controller@b01b0100 {
>  			reg = <0xb01b0100 0x100>;
>  			#power-domain-cells = <1>;
>  		};
> +
> +		dma: dma-controller@b0260000 {
> +			compatible = "actions,s500-dma";
> +			reg = <0xb0260000 0xd00>;
> +			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			dma-channels = <12>;
> +			dma-requests = <46>;
> +			clocks = <&cmu CLK_DMAC>;
> +			power-domains = <&sps S500_PD_DMA>;
> +		};
>  	};
>  };
> -- 
> 2.29.2
> 

Re: [PATCH v2 07/18] arm: dts: owl-s500: Add pinctrl & GPIO support

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:01AM +0200, Cristian Ciocaltea wrote:
> Add pinctrl node for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 449e9807c4ec..b16172615db0 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -6,6 +6,7 @@
>   */
>  
>  #include <dt-bindings/clock/actions,s500-cmu.h>
> +#include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/owl-s500-powergate.h>
>  #include <dt-bindings/reset/actions,s500-reset.h>
> @@ -208,6 +209,25 @@ sps: power-controller@b01b0100 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		pinctrl: pinctrl@b01b0000 {
> +			compatible = "actions,s500-pinctrl";
> +			reg = <0xb01b0000 0x40>, /* GPIO */
> +			      <0xb01b0040 0x10>, /* Multiplexing Control */
> +			      <0xb01b0060 0x18>, /* PAD Control */
> +			      <0xb01b0080 0xc>;  /* PAD Drive Capacity */
> +			clocks = <&cmu CLK_GPIO>;
> +			gpio-controller;
> +			gpio-ranges = <&pinctrl 0 0 132>;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
> +				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
> +				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
> +				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
> +				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
> +		};
> +
>  		dma: dma-controller@b0260000 {
>  			compatible = "actions,s500-dma";
>  			reg = <0xb0260000 0xd00>;
> -- 
> 2.29.2
> 

Re: [PATCH v2 09/18] arm: dts: owl-s500: Add MMC support

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:03AM +0200, Cristian Ciocaltea wrote:
> Add MMC controller nodes for Actions Semi S500 SoC, in order to
> facilitate access to SD/EMMC/SDIO cards.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index b16172615db0..7af7c9e1119d 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 {
>  			clocks = <&cmu CLK_DMAC>;
>  			power-domains = <&sps S500_PD_DMA>;
>  		};
> +
> +		mmc0: mmc@b0230000 {
> +			compatible = "actions,s500-mmc", "actions,owl-mmc";
> +			reg = <0xb0230000 0x38>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_SD0>;
> +			resets = <&cmu RESET_SD0>;
> +			dmas = <&dma 2>;
> +			dma-names = "mmc";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@b0234000 {
> +			compatible = "actions,s500-mmc", "actions,owl-mmc";
> +			reg = <0xb0234000 0x38>;
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_SD1>;
> +			resets = <&cmu RESET_SD1>;
> +			dmas = <&dma 3>;
> +			dma-names = "mmc";
> +			status = "disabled";
> +		};
> +
> +		mmc2: mmc@b0238000 {
> +			compatible = "actions,s500-mmc", "actions,owl-mmc";
> +			reg = <0xb0238000 0x38>;
> +			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_SD2>;
> +			resets = <&cmu RESET_SD2>;
> +			dmas = <&dma 4>;
> +			dma-names = "mmc";
> +			status = "disabled";
> +		};
>  	};
>  };
> -- 
> 2.29.2
> 

Re: [PATCH v2 12/18] i2c: owl: Add compatible for the Actions Semi S500 I2C controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:06AM +0200, Cristian Ciocaltea wrote:
> Add S500 variant to the list of devices supported by the Actions Semi
> Owl I2C driver.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/i2c/busses/i2c-owl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> index 5cf5a119a6ad..98882fe4e965 100644
> --- a/drivers/i2c/busses/i2c-owl.c
> +++ b/drivers/i2c/busses/i2c-owl.c
> @@ -508,6 +508,7 @@ static int owl_i2c_probe(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id owl_i2c_of_match[] = {
> +	{ .compatible = "actions,s500-i2c" },
>  	{ .compatible = "actions,s700-i2c" },
>  	{ .compatible = "actions,s900-i2c" },
>  	{ /* sentinel */ }
> -- 
> 2.29.2
> 

Re: [PATCH v2 13/18] arm: dts: owl-s500: Add I2C support

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:07AM +0200, Cristian Ciocaltea wrote:
> Add I2C controller nodes for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 7af7c9e1119d..55f8b8c2e149 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		i2c0: i2c@b0170000 {
> +			compatible = "actions,s500-i2c";
> +			reg = <0xb0170000 0x4000>;
> +			clocks = <&cmu CLK_I2C0>;
> +			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@b0174000 {
> +			compatible = "actions,s500-i2c";
> +			reg = <0xb0174000 0x4000>;
> +			clocks = <&cmu CLK_I2C1>;
> +			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@b0178000 {
> +			compatible = "actions,s500-i2c";
> +			reg = <0xb0178000 0x4000>;
> +			clocks = <&cmu CLK_I2C2>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@b017c000 {
> +			compatible = "actions,s500-i2c";
> +			reg = <0xb017c000 0x4000>;
> +			clocks = <&cmu CLK_I2C3>;
> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		timer: timer@b0168000 {
>  			compatible = "actions,s500-timer";
>  			reg = <0xb0168000 0x8000>;
> -- 
> 2.29.2
> 

Re: [PATCH v2 14/18] arm: dts: owl-s500: Add SIRQ controller

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:08AM +0200, Cristian Ciocaltea wrote:
> Add SIRQ controller node for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 55f8b8c2e149..cd635f222d26 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -233,6 +233,16 @@ i2c3: i2c@b017c000 {
>  			status = "disabled";
>  		};
>  
> +		sirq: interrupt-controller@b01b0200 {
> +			compatible = "actions,s500-sirq";
> +			reg = <0xb01b0200 0x4>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
> +				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
> +				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
> +		};
> +
>  		timer: timer@b0168000 {
>  			compatible = "actions,s500-timer";
>  			reg = <0xb0168000 0x8000>;
> -- 
> 2.29.2
> 

Re: [PATCH v2 15/18] arm: dts: owl-s500-roseapplepi: Use UART clock from CMU

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:09AM +0200, Cristian Ciocaltea wrote:
> Remove the UART fixed clock for RoseapplePi SBC and switch to using
> the clock provided by CMU.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Please club this patch with the one adding CMU clock.

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index a2087e617cb2..800edf5d2d12 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -25,12 +25,6 @@ memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000>; /* 2GB */
>  	};
> -
> -	uart2_clk: uart2-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>  };
>  
>  &twd_timer {
> @@ -43,5 +37,4 @@ &timer {
>  
>  &uart2 {
>  	status = "okay";
> -	clocks = <&uart2_clk>;
>  };
> -- 
> 2.29.2
> 

Re: [PATCH v2 16/18] arm: dts: owl-s500-roseapplepi: Add uSD support

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:10AM +0200, Cristian Ciocaltea wrote:
> Add uSD support for RoseapplePi SBC using a fixed regulator as a
> temporary solution until PMIC support becomes available.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index 800edf5d2d12..fe9ae3619422 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -14,6 +14,7 @@ / {
>  	model = "Roseapple Pi";
>  
>  	aliases {
> +		mmc0 = &mmc0;
>  		serial2 = &uart2;
>  	};
>  
> @@ -25,6 +26,55 @@ memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000>; /* 2GB */
>  	};
> +
> +	/* Fixed regulator used in the absence of PMIC */
> +	sd_vcc: sd-vcc {

Is this the exact name in the schematics?

Thanks,
Mani

> +		compatible = "regulator-fixed";
> +		regulator-name = "fixed-3.1V";
> +		regulator-min-microvolt = <3100000>;
> +		regulator-max-microvolt = <3100000>;
> +		regulator-always-on;
> +	};
> +};
> +
> +&pinctrl {
> +	mmc0_pins: mmc0-pins {
> +		pinmux {
> +			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> +				 "sd0_cmd_mfp", "sd0_clk_mfp";
> +			function = "sd0";
> +		};
> +
> +		drv-pinconf {
> +			groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
> +			drive-strength = <8>;
> +		};
> +
> +		bias0-pinconf {
> +			pins = "sd0_d0", "sd0_d1", "sd0_d2",
> +			       "sd0_d3", "sd0_cmd";
> +			bias-pull-up;
> +		};
> +
> +		bias1-pinconf {
> +			pins = "sd0_clk";
> +			bias-pull-down;
> +		};
> +	};
> +};
> +
> +/* uSD */
> +&mmc0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc0_pins>;
> +	no-sdio;
> +	no-mmc;
> +	no-1-8-v;
> +	cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
> +	bus-width = <4>;
> +	vmmc-supply = <&sd_vcc>;
> +	vqmmc-supply = <&sd_vcc>;
>  };
>  
>  &twd_timer {
> -- 
> 2.29.2
> 

Re: [PATCH v2 17/18] arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:11AM +0200, Cristian Ciocaltea wrote:
> Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC.
> For the moment enable only I2C0, which is used by the ATC2603C PMIC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Earlier we used to add "_default" suffix for the pin groups to
differentiate between active and sleep states. But I guess we can just
keep the suffix away until we hit usecase.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index fe9ae3619422..ff91561ca99c 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -37,7 +37,51 @@ sd_vcc: sd-vcc {
>  	};
>  };
>  
> +&i2c0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c0_pins>;
> +};
> +
> +&i2c1 {
> +	status = "disabled";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c1_pins>;
> +};
> +
> +&i2c2 {
> +	status = "disabled";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c2_pins>;
> +};
> +
>  &pinctrl {
> +	i2c0_pins: i2c0-pins {
> +		pinmux {
> +			groups = "i2c0_mfp";
> +			function = "i2c0";
> +		};
> +
> +		pinconf {
> +			pins = "i2c0_sclk", "i2c0_sdata";
> +			bias-pull-up;
> +		};
> +	};
> +
> +	i2c1_pins: i2c1-pins {
> +		pinconf {
> +			pins = "i2c1_sclk", "i2c1_sdata";
> +			bias-pull-up;
> +		};
> +	};
> +
> +	i2c2_pins: i2c2-pins {
> +		pinconf {
> +			pins = "i2c2_sclk", "i2c2_sdata";
> +			bias-pull-up;
> +		};
> +	};
> +
>  	mmc0_pins: mmc0-pins {
>  		pinmux {
>  			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> -- 
> 2.29.2
> 

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Manivannan Sadhasivam]

On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
> Add the linux-actions mailing list for the Actions Semi architecture.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

There was a patch from me for this change but I don't mind taking yours
as long as we keep the list updated :)

I have just one comment below, with that fixed:

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a85c1881cf07..8428aba52581 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
>  M:	Andreas Färber <afaerber@suse.de>
>  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

No need to keep the generic list, please remove.

Thanks,
Mani

> +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/arm/actions.yaml
>  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> -- 
> 2.29.2
> 

Re: [PATCH v2 01/18] arm: dts: owl-s500: Add Clock Management Unit

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 12:52:12PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:55:55AM +0200, Cristian Ciocaltea wrote:
> > Add Clock Management Unit for Actions Semi S500 SoC.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks for taking the time to review this patch series!

Kind regards,
Cristi

> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> > index 1dbe4e8b38ac..5d5ad9db549b 100644
> > --- a/arch/arm/boot/dts/owl-s500.dtsi
> > +++ b/arch/arm/boot/dts/owl-s500.dtsi
> > @@ -5,6 +5,7 @@
> >   * Copyright (c) 2016-2017 Andreas Färber
> >   */
> >  
> > +#include <dt-bindings/clock/actions,s500-cmu.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/power/owl-s500-powergate.h>
> >  
> > @@ -70,6 +71,12 @@ hosc: hosc {
> >  		#clock-cells = <0>;
> >  	};
> >  
> > +	losc: losc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <32768>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> >  	soc {
> >  		compatible = "simple-bus";
> >  		#address-cells = <1>;
> > @@ -169,6 +176,13 @@ uart6: serial@b012c000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		cmu: clock-controller@b0160000 {
> > +			compatible = "actions,s500-cmu";
> > +			reg = <0xb0160000 0x8000>;
> > +			clocks = <&hosc>, <&losc>;
> > +			#clock-cells = <1>;
> > +		};
> > +
> >  		timer: timer@b0168000 {
> >  			compatible = "actions,s500-timer";
> >  			reg = <0xb0168000 0x8000>;
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 02/18] arm: dts: owl-s500: Set CMU clocks for UARTs

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 12:55:13PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:55:56AM +0200, Cristian Ciocaltea wrote:
> > Set Clock Management Unit clocks for the UART nodes of Actions Semi
> > S500 SoCs.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Also in this patch itself, you need to remove the dummy "uart3_clk" from
> S500 dts. With that,

I have prepared the updated patch with the requested changes, including
also the merge of the RoseapplePi related patch (no. 15 in this series).

Thanks,
Cristi

> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> > index 5d5ad9db549b..ac3d04c75dd5 100644
> > --- a/arch/arm/boot/dts/owl-s500.dtsi
> > +++ b/arch/arm/boot/dts/owl-s500.dtsi
> > @@ -131,6 +131,7 @@ uart0: serial@b0120000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb0120000 0x2000>;
> >  			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART0>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -138,6 +139,7 @@ uart1: serial@b0122000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb0122000 0x2000>;
> >  			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART1>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -145,6 +147,7 @@ uart2: serial@b0124000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb0124000 0x2000>;
> >  			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART2>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -152,6 +155,7 @@ uart3: serial@b0126000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb0126000 0x2000>;
> >  			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART3>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -159,6 +163,7 @@ uart4: serial@b0128000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb0128000 0x2000>;
> >  			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART4>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -166,6 +171,7 @@ uart5: serial@b012a000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb012a000 0x2000>;
> >  			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART5>;
> >  			status = "disabled";
> >  		};
> >  
> > @@ -173,6 +179,7 @@ uart6: serial@b012c000 {
> >  			compatible = "actions,s500-uart", "actions,owl-uart";
> >  			reg = <0xb012c000 0x2000>;
> >  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cmu CLK_UART6>;
> >  			status = "disabled";
> >  		};
> >  
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 12:59:45PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:55:58AM +0200, Cristian Ciocaltea wrote:
> > Add a new compatible string corresponding to the DMA controller found
> > in the S500 variant of the Actions Semi Owl SoCs family.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> > index 256d62af2c64..f085f0e42d2c 100644
> > --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml
> > +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
> > @@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller
> >  
> >  description: |
> >    The OWL DMA is a general-purpose direct memory access controller capable of
> > -  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
> > -  respectively.
> > +  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
> > +  independent DMA channels for the S500 and S900 SoC variants.
> >  
> >  maintainers:
> >    - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > @@ -22,6 +22,7 @@ properties:
> >      enum:
> >        - actions,s900-dma
> >        - actions,s700-dma
> > +      - actions,s500-dma
> 
> I think we should order the entries now...

Right, I will provide the reordered list in the upcoming revision.

> >  
> >    reg:
> >      maxItems: 1
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 05/18] dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 01:00:45PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:55:59AM +0200, Cristian Ciocaltea wrote:
> > The DMA controller present on the Actions Semi S500 SoC is compatible
> > with the S900 variant, so add it to the list of devices supported by
> > the Actions Semi Owl DMA driver.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> I hope that you have verified both Memcpy and Slave transfers...

I have been using 'dmatest' module as documented in:
https://www.kernel.org/doc/html/latest/driver-api/dmaengine/dmatest.html

I tested all the available channels and could not find any signs of
possible issues. Bellow is an excerpt from the kernel ring buffer:

[ 2661.884680] dmatest: dma0chan1-copy0: summary 300 tests, 0 failures 1653.48 iops 13249 KB/s (0)
[ 2661.886567] dmatest: dma0chan2-copy0: summary 300 tests, 0 failures 1684.40 iops 12846 KB/s (0)
[ 2661.888448] dmatest: dma0chan3-copy0: summary 300 tests, 0 failures 1730.62 iops 13648 KB/s (0)

Should I perform some additional tests?

Thanks,
Cristi

> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> Thanks,
> Mani
> 
> > ---
> >  drivers/dma/owl-dma.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
> > index 9fede32641e9..54e509de66e2 100644
> > --- a/drivers/dma/owl-dma.c
> > +++ b/drivers/dma/owl-dma.c
> > @@ -1082,6 +1082,7 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
> >  static const struct of_device_id owl_dma_match[] = {
> >  	{ .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
> >  	{ .compatible = "actions,s700-dma", .data = (void *)S700_DMA,},
> > +	{ .compatible = "actions,s500-dma", .data = (void *)S900_DMA,},
> >  	{ /* sentinel */ },
> >  };
> >  MODULE_DEVICE_TABLE(of, owl_dma_match);
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 15/18] arm: dts: owl-s500-roseapplepi: Use UART clock from CMU

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 01:06:50PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:56:09AM +0200, Cristian Ciocaltea wrote:
> > Remove the UART fixed clock for RoseapplePi SBC and switch to using
> > the clock provided by CMU.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Please club this patch with the one adding CMU clock.

Done.

Thanks,
Cristi

> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 -------
> >  1 file changed, 7 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > index a2087e617cb2..800edf5d2d12 100644
> > --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > @@ -25,12 +25,6 @@ memory@0 {
> >  		device_type = "memory";
> >  		reg = <0x0 0x80000000>; /* 2GB */
> >  	};
> > -
> > -	uart2_clk: uart2-clk {
> > -		compatible = "fixed-clock";
> > -		clock-frequency = <921600>;
> > -		#clock-cells = <0>;
> > -	};
> >  };
> >  
> >  &twd_timer {
> > @@ -43,5 +37,4 @@ &timer {
> >  
> >  &uart2 {
> >  	status = "okay";
> > -	clocks = <&uart2_clk>;
> >  };
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 16/18] arm: dts: owl-s500-roseapplepi: Add uSD support

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 01:08:51PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:56:10AM +0200, Cristian Ciocaltea wrote:
> > Add uSD support for RoseapplePi SBC using a fixed regulator as a
> > temporary solution until PMIC support becomes available.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> >  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
> >  1 file changed, 50 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > index 800edf5d2d12..fe9ae3619422 100644
> > --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > @@ -14,6 +14,7 @@ / {
> >  	model = "Roseapple Pi";
> >  
> >  	aliases {
> > +		mmc0 = &mmc0;
> >  		serial2 = &uart2;
> >  	};
> >  
> > @@ -25,6 +26,55 @@ memory@0 {
> >  		device_type = "memory";
> >  		reg = <0x0 0x80000000>; /* 2GB */
> >  	};
> > +
> > +	/* Fixed regulator used in the absence of PMIC */
> > +	sd_vcc: sd-vcc {
> 
> Is this the exact name in the schematics?

Yes, it is referred as "SD_VCC". Once the support for the ATC260x PMIC
will be available, the following item will be present in the regulators
list:

  sd_vcc: switchldo1 {
	regulator-name = "SD_VCC";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
  };

Thanks,
Cristi

> Thanks,
> Mani
> 
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "fixed-3.1V";
> > +		regulator-min-microvolt = <3100000>;
> > +		regulator-max-microvolt = <3100000>;
> > +		regulator-always-on;
> > +	};
> > +};
> > +
> > +&pinctrl {
> > +	mmc0_pins: mmc0-pins {
> > +		pinmux {
> > +			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> > +				 "sd0_cmd_mfp", "sd0_clk_mfp";
> > +			function = "sd0";
> > +		};
> > +
> > +		drv-pinconf {
> > +			groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
> > +			drive-strength = <8>;
> > +		};
> > +
> > +		bias0-pinconf {
> > +			pins = "sd0_d0", "sd0_d1", "sd0_d2",
> > +			       "sd0_d3", "sd0_cmd";
> > +			bias-pull-up;
> > +		};
> > +
> > +		bias1-pinconf {
> > +			pins = "sd0_clk";
> > +			bias-pull-down;
> > +		};
> > +	};
> > +};
> > +
> > +/* uSD */
> > +&mmc0 {
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&mmc0_pins>;
> > +	no-sdio;
> > +	no-mmc;
> > +	no-1-8-v;
> > +	cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
> > +	bus-width = <4>;
> > +	vmmc-supply = <&sd_vcc>;
> > +	vqmmc-supply = <&sd_vcc>;
> >  };
> >  
> >  &twd_timer {
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 17/18] arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 01:11:08PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:56:11AM +0200, Cristian Ciocaltea wrote:
> > Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC.
> > For the moment enable only I2C0, which is used by the ATC2603C PMIC.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Earlier we used to add "_default" suffix for the pin groups to
> differentiate between active and sleep states. But I guess we can just
> keep the suffix away until we hit usecase.

I had actually used this suffix when I submitted the first revision of
the S500 pinctrl driver, but I dropped it later in the review process
since it was considered an uncommon approach:
https://lore.kernel.org/lkml/CAL_Jsq+8bX5duv=116e=hve1L-h8a=5quqCHVtSAs4PjK6xc1w@mail.gmail.com/

Thanks,
Cristi

> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > index fe9ae3619422..ff91561ca99c 100644
> > --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > @@ -37,7 +37,51 @@ sd_vcc: sd-vcc {
> >  	};
> >  };
> >  
> > +&i2c0 {
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c0_pins>;
> > +};
> > +
> > +&i2c1 {
> > +	status = "disabled";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c1_pins>;
> > +};
> > +
> > +&i2c2 {
> > +	status = "disabled";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c2_pins>;
> > +};
> > +
> >  &pinctrl {
> > +	i2c0_pins: i2c0-pins {
> > +		pinmux {
> > +			groups = "i2c0_mfp";
> > +			function = "i2c0";
> > +		};
> > +
> > +		pinconf {
> > +			pins = "i2c0_sclk", "i2c0_sdata";
> > +			bias-pull-up;
> > +		};
> > +	};
> > +
> > +	i2c1_pins: i2c1-pins {
> > +		pinconf {
> > +			pins = "i2c1_sclk", "i2c1_sdata";
> > +			bias-pull-up;
> > +		};
> > +	};
> > +
> > +	i2c2_pins: i2c2-pins {
> > +		pinconf {
> > +			pins = "i2c2_sclk", "i2c2_sdata";
> > +			bias-pull-up;
> > +		};
> > +	};
> > +
> >  	mmc0_pins: mmc0-pins {
> >  		pinmux {
> >  			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Cristian Ciocaltea]

On Sat, Nov 28, 2020 at 01:13:50PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
> > Add the linux-actions mailing list for the Actions Semi architecture.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> There was a patch from me for this change but I don't mind taking yours
> as long as we keep the list updated :)

Sorry about that, I often forget to manually append this mailing list
before submitting related patches and therefore I considered this is
a good opportunity to have this issue fixed once and for all.. :)

> I have just one comment below, with that fixed:
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> > ---
> >  MAINTAINERS | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index a85c1881cf07..8428aba52581 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
> >  M:	Andreas Färber <afaerber@suse.de>
> >  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> 
> No need to keep the generic list, please remove.

Done, thanks!

> Thanks,
> Mani
> 
> > +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
> >  S:	Maintained
> >  F:	Documentation/devicetree/bindings/arm/actions.yaml
> >  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Andreas Färber]

On 29.11.20 20:48, Cristian Ciocaltea wrote:
> On Sat, Nov 28, 2020 at 01:13:50PM +0530, Manivannan Sadhasivam wrote:
>> On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
>>> Add the linux-actions mailing list for the Actions Semi architecture.
>>>
>>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
>>
>> There was a patch from me for this change but I don't mind taking yours
>> as long as we keep the list updated :)
> 
> Sorry about that, I often forget to manually append this mailing list
> before submitting related patches and therefore I considered this is
> a good opportunity to have this issue fixed once and for all.. :)
> 
>> I have just one comment below, with that fixed:
>>
>> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>
>>> ---
>>>  MAINTAINERS | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index a85c1881cf07..8428aba52581 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
>>>  M:	Andreas Färber <afaerber@suse.de>
>>>  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>>
>> No need to keep the generic list, please remove.

Why? They're not mutually exclusive.

Regards,
Andreas

> 
> Done, thanks!
> 
>> Thanks,
>> Mani
>>
>>> +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
>>>  S:	Maintained
>>>  F:	Documentation/devicetree/bindings/arm/actions.yaml
>>>  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
>>> -- 
>>> 2.29.2
>>>


-- 
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer
HRB 36809 (AG Nürnberg)

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Manivannan Sadhasivam]

On Mon, Nov 30, 2020 at 01:54:45AM +0100, Andreas Färber wrote:
> On 29.11.20 20:48, Cristian Ciocaltea wrote:
> > On Sat, Nov 28, 2020 at 01:13:50PM +0530, Manivannan Sadhasivam wrote:
> >> On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
> >>> Add the linux-actions mailing list for the Actions Semi architecture.
> >>>
> >>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> >>
> >> There was a patch from me for this change but I don't mind taking yours
> >> as long as we keep the list updated :)
> > 
> > Sorry about that, I often forget to manually append this mailing list
> > before submitting related patches and therefore I considered this is
> > a good opportunity to have this issue fixed once and for all.. :)
> > 
> >> I have just one comment below, with that fixed:
> >>
> >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >>
> >>> ---
> >>>  MAINTAINERS | 1 +
> >>>  1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/MAINTAINERS b/MAINTAINERS
> >>> index a85c1881cf07..8428aba52581 100644
> >>> --- a/MAINTAINERS
> >>> +++ b/MAINTAINERS
> >>> @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
> >>>  M:	Andreas Färber <afaerber@suse.de>
> >>>  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >>>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> >>
> >> No need to keep the generic list, please remove.
> 
> Why? They're not mutually exclusive.
> 

Yes but why do we want to spam it? Currently we don't archive actions tree in
lore but I can do that.

Thanks,
Mani

> Regards,
> Andreas
> 
> > 
> > Done, thanks!
> > 
> >> Thanks,
> >> Mani
> >>
> >>> +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
> >>>  S:	Maintained
> >>>  F:	Documentation/devicetree/bindings/arm/actions.yaml
> >>>  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> >>> -- 
> >>> 2.29.2
> >>>
> 
> 
> -- 
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer
> HRB 36809 (AG Nürnberg)

Re: [PATCH v2 16/18] arm: dts: owl-s500-roseapplepi: Add uSD support

[Manivannan Sadhasivam]

On Sun, Nov 29, 2020 at 08:35:32PM +0200, Cristian Ciocaltea wrote:
> On Sat, Nov 28, 2020 at 01:08:51PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Nov 20, 2020 at 01:56:10AM +0200, Cristian Ciocaltea wrote:
> > > Add uSD support for RoseapplePi SBC using a fixed regulator as a
> > > temporary solution until PMIC support becomes available.
> > > 
> > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > > ---
> > >  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
> > >  1 file changed, 50 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > > index 800edf5d2d12..fe9ae3619422 100644
> > > --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > > @@ -14,6 +14,7 @@ / {
> > >  	model = "Roseapple Pi";
> > >  
> > >  	aliases {
> > > +		mmc0 = &mmc0;
> > >  		serial2 = &uart2;
> > >  	};
> > >  
> > > @@ -25,6 +26,55 @@ memory@0 {
> > >  		device_type = "memory";
> > >  		reg = <0x0 0x80000000>; /* 2GB */
> > >  	};
> > > +
> > > +	/* Fixed regulator used in the absence of PMIC */
> > > +	sd_vcc: sd-vcc {
> > 
> > Is this the exact name in the schematics?
> 
> Yes, it is referred as "SD_VCC". Once the support for the ATC260x PMIC
> will be available, the following item will be present in the regulators
> list:
> 
>   sd_vcc: switchldo1 {
> 	regulator-name = "SD_VCC";
> 	regulator-min-microvolt = <3000000>;
> 	regulator-max-microvolt = <3300000>;
> 	regulator-always-on;
> 	regulator-boot-on;
>   };

okay, looks fine to me.

Thanks,
Mani

> 
> Thanks,
> Cristi
> 
> > Thanks,
> > Mani
> > 
> > > +		compatible = "regulator-fixed";
> > > +		regulator-name = "fixed-3.1V";
> > > +		regulator-min-microvolt = <3100000>;
> > > +		regulator-max-microvolt = <3100000>;
> > > +		regulator-always-on;
> > > +	};
> > > +};
> > > +
> > > +&pinctrl {
> > > +	mmc0_pins: mmc0-pins {
> > > +		pinmux {
> > > +			groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> > > +				 "sd0_cmd_mfp", "sd0_clk_mfp";
> > > +			function = "sd0";
> > > +		};
> > > +
> > > +		drv-pinconf {
> > > +			groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
> > > +			drive-strength = <8>;
> > > +		};
> > > +
> > > +		bias0-pinconf {
> > > +			pins = "sd0_d0", "sd0_d1", "sd0_d2",
> > > +			       "sd0_d3", "sd0_cmd";
> > > +			bias-pull-up;
> > > +		};
> > > +
> > > +		bias1-pinconf {
> > > +			pins = "sd0_clk";
> > > +			bias-pull-down;
> > > +		};
> > > +	};
> > > +};
> > > +
> > > +/* uSD */
> > > +&mmc0 {
> > > +	status = "okay";
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&mmc0_pins>;
> > > +	no-sdio;
> > > +	no-mmc;
> > > +	no-1-8-v;
> > > +	cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
> > > +	bus-width = <4>;
> > > +	vmmc-supply = <&sd_vcc>;
> > > +	vqmmc-supply = <&sd_vcc>;
> > >  };
> > >  
> > >  &twd_timer {
> > > -- 
> > > 2.29.2
> > > 

Re: [PATCH v2 05/18] dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller

[Manivannan Sadhasivam]

On Sun, Nov 29, 2020 at 08:24:21PM +0200, Cristian Ciocaltea wrote:
> On Sat, Nov 28, 2020 at 01:00:45PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Nov 20, 2020 at 01:55:59AM +0200, Cristian Ciocaltea wrote:
> > > The DMA controller present on the Actions Semi S500 SoC is compatible
> > > with the S900 variant, so add it to the list of devices supported by
> > > the Actions Semi Owl DMA driver.
> > > 
> > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > 
> > I hope that you have verified both Memcpy and Slave transfers...
> 
> I have been using 'dmatest' module as documented in:
> https://www.kernel.org/doc/html/latest/driver-api/dmaengine/dmatest.html
> 
> I tested all the available channels and could not find any signs of
> possible issues. Bellow is an excerpt from the kernel ring buffer:
> 
> [ 2661.884680] dmatest: dma0chan1-copy0: summary 300 tests, 0 failures 1653.48 iops 13249 KB/s (0)
> [ 2661.886567] dmatest: dma0chan2-copy0: summary 300 tests, 0 failures 1684.40 iops 12846 KB/s (0)
> [ 2661.888448] dmatest: dma0chan3-copy0: summary 300 tests, 0 failures 1730.62 iops 13648 KB/s (0)
> 
> Should I perform some additional tests?
> 

Nope, this is sufficient. Since you have tested slave transfer with MMC driver,
running dmatest for memcpy is fine.

Thanks,
Mani

> Thanks,
> Cristi
> 
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > 
> > Thanks,
> > Mani
> > 
> > > ---
> > >  drivers/dma/owl-dma.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
> > > index 9fede32641e9..54e509de66e2 100644
> > > --- a/drivers/dma/owl-dma.c
> > > +++ b/drivers/dma/owl-dma.c
> > > @@ -1082,6 +1082,7 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
> > >  static const struct of_device_id owl_dma_match[] = {
> > >  	{ .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
> > >  	{ .compatible = "actions,s700-dma", .data = (void *)S700_DMA,},
> > > +	{ .compatible = "actions,s500-dma", .data = (void *)S900_DMA,},
> > >  	{ /* sentinel */ },
> > >  };
> > >  MODULE_DEVICE_TABLE(of, owl_dma_match);
> > > -- 
> > > 2.29.2
> > > 

Re: [PATCH v2 00/18] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

[Manivannan Sadhasivam]

Hi Cristi,

On Fri, Nov 20, 2020 at 01:55:54AM +0200, Cristian Ciocaltea wrote:
> Hi,
> 
> This patchset brings a series of improvements for the Actions Semi S500
> SoCs family, by adding support for Clock & Reset Management Units, DMA,
> MMC, I2C & SIRQ controllers.
> 
> Please note the patches consist mostly of DTS and bindings/compatibles
> changes, since all the work they depend on has been already merged,
> i.e. clock fixes/additions, pinctrl driver, sirq driver.
> 
> For the moment, I have only enabled the features I could test on
> RoseapplePi SBC.
> 

I was hoping to apply this series for v5.11 but we ran out of time. So expect
this series to be in v5.12.

Thanks,
Mani

> Thanks,
> Cristi
> 
> Changes in v2:
> - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
> - Added support for the SIRQ controller
> - Added new entries in MAINTAINERS
> - Updated naming of some patches in v1
> 
> Cristian Ciocaltea (18):
>   arm: dts: owl-s500: Add Clock Management Unit
>   arm: dts: owl-s500: Set CMU clocks for UARTs
>   arm: dts: owl-s500: Add Reset controller
>   dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
>   dmaengine: owl: Add compatible for the Actions Semi S500 DMA
>     controller
>   arm: dts: owl-s500: Add DMA controller
>   arm: dts: owl-s500: Add pinctrl & GPIO support
>   dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
>   arm: dts: owl-s500: Add MMC support
>   dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
>   MAINTAINERS: Update entry for Actions Semi Owl I2C binding
>   i2c: owl: Add compatible for the Actions Semi S500 I2C controller
>   arm: dts: owl-s500: Add I2C support
>   arm: dts: owl-s500: Add SIRQ controller
>   arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
>   arm: dts: owl-s500-roseapplepi: Add uSD support
>   arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
>   MAINTAINERS: Add linux-actions ML for Actions Semi Arch
> 
>  .../devicetree/bindings/dma/owl-dma.yaml      |   5 +-
>  .../devicetree/bindings/i2c/i2c-owl.txt       |  29 ----
>  .../devicetree/bindings/i2c/i2c-owl.yaml      |  62 ++++++++
>  .../devicetree/bindings/mmc/owl-mmc.yaml      |   4 +-
>  MAINTAINERS                                   |   3 +-
>  arch/arm/boot/dts/owl-s500-roseapplepi.dts    |  97 +++++++++++-
>  arch/arm/boot/dts/owl-s500.dtsi               | 140 ++++++++++++++++++
>  drivers/dma/owl-dma.c                         |   1 +
>  drivers/i2c/busses/i2c-owl.c                  |   1 +
>  9 files changed, 304 insertions(+), 38 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml
> 
> -- 
> 2.29.2
> 

Re: [PATCH v2 00/18] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

[Cristian Ciocaltea]

Hi Mani,

On Sat, Dec 05, 2020 at 11:41:15AM +0530, Manivannan Sadhasivam wrote:
> Hi Cristi,
> 
> On Fri, Nov 20, 2020 at 01:55:54AM +0200, Cristian Ciocaltea wrote:
> > Hi,
> > 
> > This patchset brings a series of improvements for the Actions Semi S500
> > SoCs family, by adding support for Clock & Reset Management Units, DMA,
> > MMC, I2C & SIRQ controllers.
> > 
> > Please note the patches consist mostly of DTS and bindings/compatibles
> > changes, since all the work they depend on has been already merged,
> > i.e. clock fixes/additions, pinctrl driver, sirq driver.
> > 
> > For the moment, I have only enabled the features I could test on
> > RoseapplePi SBC.
> > 
> 
> I was hoping to apply this series for v5.11 but we ran out of time. So expect
> this series to be in v5.12.

No problem, thanks a lot for taking care of this!

Kind regards,
Cristi

> Thanks,
> Mani
> 
> > Thanks,
> > Cristi
> > 
> > Changes in v2:
> > - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
> > - Added support for the SIRQ controller
> > - Added new entries in MAINTAINERS
> > - Updated naming of some patches in v1
> > 
> > Cristian Ciocaltea (18):
> >   arm: dts: owl-s500: Add Clock Management Unit
> >   arm: dts: owl-s500: Set CMU clocks for UARTs
> >   arm: dts: owl-s500: Add Reset controller
> >   dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
> >   dmaengine: owl: Add compatible for the Actions Semi S500 DMA
> >     controller
> >   arm: dts: owl-s500: Add DMA controller
> >   arm: dts: owl-s500: Add pinctrl & GPIO support
> >   dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
> >   arm: dts: owl-s500: Add MMC support
> >   dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
> >   MAINTAINERS: Update entry for Actions Semi Owl I2C binding
> >   i2c: owl: Add compatible for the Actions Semi S500 I2C controller
> >   arm: dts: owl-s500: Add I2C support
> >   arm: dts: owl-s500: Add SIRQ controller
> >   arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
> >   arm: dts: owl-s500-roseapplepi: Add uSD support
> >   arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
> >   MAINTAINERS: Add linux-actions ML for Actions Semi Arch
> > 
> >  .../devicetree/bindings/dma/owl-dma.yaml      |   5 +-
> >  .../devicetree/bindings/i2c/i2c-owl.txt       |  29 ----
> >  .../devicetree/bindings/i2c/i2c-owl.yaml      |  62 ++++++++
> >  .../devicetree/bindings/mmc/owl-mmc.yaml      |   4 +-
> >  MAINTAINERS                                   |   3 +-
> >  arch/arm/boot/dts/owl-s500-roseapplepi.dts    |  97 +++++++++++-
> >  arch/arm/boot/dts/owl-s500.dtsi               | 140 ++++++++++++++++++
> >  drivers/dma/owl-dma.c                         |   1 +
> >  drivers/i2c/busses/i2c-owl.c                  |   1 +
> >  9 files changed, 304 insertions(+), 38 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
> >  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml
> > 
> > -- 
> > 2.29.2
> > 

Re: [PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Rob Herring]

On Fri, 20 Nov 2020 01:55:58 +0200, Cristian Ciocaltea wrote:
> Add a new compatible string corresponding to the DMA controller found
> in the S500 variant of the Actions Semi Owl SoCs family.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 10/18] dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema

[Rob Herring]

On Fri, 20 Nov 2020 01:56:04 +0200, Cristian Ciocaltea wrote:
> Convert the Actions Semi Owl I2C DT binding to a YAML schema for
> enabling DT validation.
> 
> Additionally, add a new compatible string corresponding to the I2C
> controller found in the S500 variant of the Actions Semi Owl SoCs
> family.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  .../devicetree/bindings/i2c/i2c-owl.txt       | 29 ---------
>  .../devicetree/bindings/i2c/i2c-owl.yaml      | 62 +++++++++++++++++++
>  2 files changed, 62 insertions(+), 29 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 04/18] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC

[Cristian Ciocaltea]

On Mon, Dec 07, 2020 at 04:11:07PM -0600, Rob Herring wrote:
> On Fri, 20 Nov 2020 01:55:58 +0200, Cristian Ciocaltea wrote:
> > Add a new compatible string corresponding to the DMA controller found
> > in the S500 variant of the Actions Semi Owl SoCs family.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/dma/owl-dma.yaml | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Thanks for reviewing,
Cristi

Re: [PATCH v2 10/18] dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema

[Cristian Ciocaltea]

On Mon, Dec 07, 2020 at 04:12:14PM -0600, Rob Herring wrote:
> On Fri, 20 Nov 2020 01:56:04 +0200, Cristian Ciocaltea wrote:
> > Convert the Actions Semi Owl I2C DT binding to a YAML schema for
> > enabling DT validation.
> > 
> > Additionally, add a new compatible string corresponding to the I2C
> > controller found in the S500 variant of the Actions Semi Owl SoCs
> > family.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> >  .../devicetree/bindings/i2c/i2c-owl.txt       | 29 ---------
> >  .../devicetree/bindings/i2c/i2c-owl.yaml      | 62 +++++++++++++++++++
> >  2 files changed, 62 insertions(+), 29 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
> >  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml
> > 
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Thanks for reviewing,
Cristi

Re: [PATCH v2 10/18] dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema

[Wolfram Sang]

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On Fri, Nov 20, 2020 at 01:56:04AM +0200, Cristian Ciocaltea wrote:
> Convert the Actions Semi Owl I2C DT binding to a YAML schema for
> enabling DT validation.
> 
> Additionally, add a new compatible string corresponding to the I2C
> controller found in the S500 variant of the Actions Semi Owl SoCs
> family.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH v2 11/18] MAINTAINERS: Update entry for Actions Semi Owl I2C binding

[Wolfram Sang]

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On Fri, Nov 20, 2020 at 01:56:05AM +0200, Cristian Ciocaltea wrote:
> The Actions Semi Owl I2C DT binding has been converted to YAML schema,
> therefore update accordingly the entry in MAINTAINERS.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Squashed with 10/18 and applied to for-next, thanks!


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Re: [PATCH v2 12/18] i2c: owl: Add compatible for the Actions Semi S500 I2C controller

[Wolfram Sang]

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On Fri, Nov 20, 2020 at 01:56:06AM +0200, Cristian Ciocaltea wrote:
> Add S500 variant to the list of devices supported by the Actions Semi
> Owl I2C driver.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH v2 13/18] arm: dts: owl-s500: Add I2C support

[Wolfram Sang]

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On Sat, Nov 28, 2020 at 01:05:16PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 20, 2020 at 01:56:07AM +0200, Cristian Ciocaltea wrote:
> > Add I2C controller nodes for Actions Semi S500 SoC.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

DTS changes usually go in via arm-soc, so I am not picking this unless
there is a reason to do so.


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Re: [PATCH v2 13/18] arm: dts: owl-s500: Add I2C support

[Manivannan Sadhasivam]

On Wed, Dec 09, 2020 at 09:25:06PM +0100, Wolfram Sang wrote:
> On Sat, Nov 28, 2020 at 01:05:16PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Nov 20, 2020 at 01:56:07AM +0200, Cristian Ciocaltea wrote:
> > > Add I2C controller nodes for Actions Semi S500 SoC.
> > > 
> > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > 
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> DTS changes usually go in via arm-soc, so I am not picking this unless
> there is a reason to do so.
> 

No you should not. This patch will go through actions sub tree which me or
Andreas will pick it.

Thanks,
Mani

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Cristian Ciocaltea]

On Sat, Dec 05, 2020 at 11:24:14AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Nov 30, 2020 at 01:54:45AM +0100, Andreas Färber wrote:
> > On 29.11.20 20:48, Cristian Ciocaltea wrote:
> > > On Sat, Nov 28, 2020 at 01:13:50PM +0530, Manivannan Sadhasivam wrote:
> > >> On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
> > >>> Add the linux-actions mailing list for the Actions Semi architecture.
> > >>>
> > >>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > >>
> > >> There was a patch from me for this change but I don't mind taking yours
> > >> as long as we keep the list updated :)
> > > 
> > > Sorry about that, I often forget to manually append this mailing list
> > > before submitting related patches and therefore I considered this is
> > > a good opportunity to have this issue fixed once and for all.. :)
> > > 
> > >> I have just one comment below, with that fixed:
> > >>
> > >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > >>
> > >>> ---
> > >>>  MAINTAINERS | 1 +
> > >>>  1 file changed, 1 insertion(+)
> > >>>
> > >>> diff --git a/MAINTAINERS b/MAINTAINERS
> > >>> index a85c1881cf07..8428aba52581 100644
> > >>> --- a/MAINTAINERS
> > >>> +++ b/MAINTAINERS
> > >>> @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
> > >>>  M:	Andreas Färber <afaerber@suse.de>
> > >>>  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > >>>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > >>
> > >> No need to keep the generic list, please remove.
> > 
> > Why? They're not mutually exclusive.
> > 
> 
> Yes but why do we want to spam it? Currently we don't archive actions tree in
> lore but I can do that.

Hi Mani, Andreas,

I'm going to prepare a new revision of this patch series, but I'm not
really sure how should I handle this patch: keep the 'linux-arm-kernel'
list or drop it?

Thanks and regards,
Cristi

> Thanks,
> Mani
> 
> > Regards,
> > Andreas
> > 
> > > 
> > > Done, thanks!
> > > 
> > >> Thanks,
> > >> Mani
> > >>
> > >>> +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
> > >>>  S:	Maintained
> > >>>  F:	Documentation/devicetree/bindings/arm/actions.yaml
> > >>>  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> > >>> -- 
> > >>> 2.29.2
> > >>>
> > 
> > 
> > -- 
> > SUSE Software Solutions Germany GmbH
> > Maxfeldstr. 5, 90409 Nürnberg, Germany
> > GF: Felix Imendörffer
> > HRB 36809 (AG Nürnberg)

Re: [PATCH v2 18/18] MAINTAINERS: Add linux-actions ML for Actions Semi Arch

[Manivannan Sadhasivam]

On Mon, Dec 28, 2020 at 12:43:07PM +0200, Cristian Ciocaltea wrote:
> On Sat, Dec 05, 2020 at 11:24:14AM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Nov 30, 2020 at 01:54:45AM +0100, Andreas Färber wrote:
> > > On 29.11.20 20:48, Cristian Ciocaltea wrote:
> > > > On Sat, Nov 28, 2020 at 01:13:50PM +0530, Manivannan Sadhasivam wrote:
> > > >> On Fri, Nov 20, 2020 at 01:56:12AM +0200, Cristian Ciocaltea wrote:
> > > >>> Add the linux-actions mailing list for the Actions Semi architecture.
> > > >>>
> > > >>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > > >>
> > > >> There was a patch from me for this change but I don't mind taking yours
> > > >> as long as we keep the list updated :)
> > > > 
> > > > Sorry about that, I often forget to manually append this mailing list
> > > > before submitting related patches and therefore I considered this is
> > > > a good opportunity to have this issue fixed once and for all.. :)
> > > > 
> > > >> I have just one comment below, with that fixed:
> > > >>
> > > >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > >>
> > > >>> ---
> > > >>>  MAINTAINERS | 1 +
> > > >>>  1 file changed, 1 insertion(+)
> > > >>>
> > > >>> diff --git a/MAINTAINERS b/MAINTAINERS
> > > >>> index a85c1881cf07..8428aba52581 100644
> > > >>> --- a/MAINTAINERS
> > > >>> +++ b/MAINTAINERS
> > > >>> @@ -1497,6 +1497,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
> > > >>>  M:	Andreas Färber <afaerber@suse.de>
> > > >>>  M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > >>>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > > >>
> > > >> No need to keep the generic list, please remove.
> > > 
> > > Why? They're not mutually exclusive.
> > > 
> > 
> > Yes but why do we want to spam it? Currently we don't archive actions tree in
> > lore but I can do that.
> 
> Hi Mani, Andreas,
> 
> I'm going to prepare a new revision of this patch series, but I'm not
> really sure how should I handle this patch: keep the 'linux-arm-kernel'
> list or drop it?
> 

Since Andreas seems to be in favour of keeping it, I don't object.

Thanks,
Mani

> Thanks and regards,
> Cristi
> 
> > Thanks,
> > Mani
> > 
> > > Regards,
> > > Andreas
> > > 
> > > > 
> > > > Done, thanks!
> > > > 
> > > >> Thanks,
> > > >> Mani
> > > >>
> > > >>> +L:	linux-actions@lists.infradead.org (moderated for non-subscribers)
> > > >>>  S:	Maintained
> > > >>>  F:	Documentation/devicetree/bindings/arm/actions.yaml
> > > >>>  F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> > > >>> -- 
> > > >>> 2.29.2
> > > >>>
> > > 
> > > 
> > > -- 
> > > SUSE Software Solutions Germany GmbH
> > > Maxfeldstr. 5, 90409 Nürnberg, Germany
> > > GF: Felix Imendörffer
> > > HRB 36809 (AG Nürnberg)