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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2022 06:28:50.7446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea2c156b-93ec-4387-3a8a-08da07df66c0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4748 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for using AMD Performance Monitoring Version 2 (PerfMonV2) features on upcoming processors. New CPU features are introduced for PerfMonV2 detection. New MSR definitions are added to make use of an alternative PMC management scheme based on the new PMC global control and status registers. The global control register provides the ability to start and stop multiple PMCs at the same time. This makes it possible to enable or disable all counters with a single MSR write instead of writing to the individual PMC control registers interatively under x86_pmu_{enable,disable}(). The effects can be seen when counting the same events across multiple PMCs. E.g. $ sudo perf stat -e "{cycles,instructions,cycles,instructions}" sleep 1 Before: Performance counter stats for 'sleep 1': 1013281 cycles 1452859 instructions # 1.43 insn per cycle 1023462 cycles 1461724 instructions # 1.43 insn per cycle 1.001644276 seconds time elapsed 0.001948000 seconds user 0.000000000 seconds sys After: Performance counter stats for 'sleep 1': 999165 cycles 1440456 instructions # 1.44 insn per cycle 999165 cycles 1440456 instructions # 1.44 insn per cycle 1.001879504 seconds time elapsed 0.001817000 seconds user 0.000000000 seconds sys No additional failures are seen upon running the following: * perf built-in test suite * perf_event_tests suite * rr test suite Sandipan Das (7): x86/cpufeatures: Add PerfMonV2 feature bit x86/msr: Add PerfCntrGlobal* registers perf/x86/amd/core: Detect PerfMonV2 support perf/x86/amd/core: Detect available counters perf/x86/amd/core: Add PerfMonV2 counter control perf/x86/amd/core: Add PerfMonV2 overflow handling kvm: x86/cpuid: Fix Architectural Performance Monitoring support arch/x86/events/amd/core.c | 217 ++++++++++++++++++++++++++++- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/msr-index.h | 5 + arch/x86/include/asm/perf_event.h | 8 ++ arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kvm/cpuid.c | 5 + 6 files changed, 230 insertions(+), 8 deletions(-) -- 2.32.0