From: Paolo Bonzini <pbonzini@redhat.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Joerg Roedel <joro@8bytes.org>,
Kim Phillips <kim.phillips@amd.com>,
Jim Mattson <jmattson@google.com>,
Maxim Levitsky <mlevitsk@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register
Date: Thu, 18 Nov 2021 14:23:56 +0100 [thread overview]
Message-ID: <d029d5e6-5b32-972d-943e-64264e599c3d@redhat.com> (raw)
In-Reply-To: <20211118130320.95997-1-likexu@tencent.com>
On 11/18/21 14:03, Like Xu wrote:
>
> This is because according to APM (Revision: 4.03) Figure 13-7,
> the bits [35:32] of AMD PerfEvtSeln register is a part of the
> event select encoding, which extends the EVENT_SELECT field
> from 8 bits to 12 bits.
Queued, thanks.
Paolo
next prev parent reply other threads:[~2021-11-18 13:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 13:03 [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register Like Xu
2021-11-18 13:23 ` Paolo Bonzini [this message]
2021-11-18 14:43 ` Paolo Bonzini
2022-02-12 8:39 ` Jim Mattson
2022-02-16 7:47 ` Like Xu
2022-02-25 22:26 ` Jim Mattson
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