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Thu, 8 Sep 2022 05:05:06 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-927-gf4c98c8499-fm-20220826.002-gf4c98c84 Mime-Version: 1.0 Message-Id: In-Reply-To: References: <7423117.EvYhyI6sBW@kista> <84f28dc3-3b65-ea70-4fa4-765d0c773c28@microchip.com> Date: Thu, 08 Sep 2022 11:04:45 +0200 From: "Arnd Bergmann" To: "Geert Uytterhoeven" , "Conor.Dooley" Cc: "Jernej Skrabec" , "Samuel Holland" , "Palmer Dabbelt" , "Chen-Yu Tsai" , linux-sunxi@lists.linux.dev, "Paul Walmsley" , "Albert Ou" , linux-riscv , "Rob Herring" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "Linux Kernel Mailing List" , "Krzysztof Kozlowski" , "Olof Johansson" Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 8, 2022, at 9:00 AM, Geert Uytterhoeven wrote: > On Wed, Sep 7, 2022 at 10:43 PM wrote: >> On 06/09/2022 21:29, Jernej =C5=A0krabec wrote: >> > Dne =C4=8Detrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dab= belt napisal(a): >> >> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), samuel@sholland.org wrot= e: >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts cr= eate >> >>> mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi c= reate >> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.1= 4.dts >> >>> create mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts c= reate >> >>> mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.= dts >> >>> create mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.= dts >> >>> create mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi = create >> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-do= ck.dts >> >>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-liche= e-rv.dts >> >>> create mode 100644 >> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts creat= e mode >> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create = mode >> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi >> >> >> >> I'm assuming these are aimed at the RISC-V tree? I'm generally OK= with >> >> that, though the DT folks have pointed out a handful of issues tha= t look >> >> pretty reasonable to me. >> > >> > DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this= be handled >> > differently for RISC-V? >> >> Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuf= f gets >> picked directly by him as it has no clear "owner". I think it would b= e nice >> to be consistent for the new {renesas,sunxi} stuff and send those via= vendor >> trees to Palmer too. Just my 2 cents... > > Wasn't the intention behind the rename s/arm-soc/soc/ to start > accepting PRs for non-arm DT, too? > Especially if we start having dependencies due to riscv DTS files > including arm64 DTS snippets through scripts/dtc/include-prefixes/arm6= 4/. Yes, absolutely. My impression was that most architecture maintainers prefer to handle the SoC support themselves, and I would not want to step on anyone's toes with this, but I'm definitely happy to take pull requests for dts files etc on any architecture if that helps. Arnd