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From: "Lendacky, Thomas" <Thomas.Lendacky@amd.com>
To: Pu Wen <puwen@hygon.cn>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>, "bp@alien8.de" <bp@alien8.de>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"helgaas@kernel.org" <helgaas@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v6 07/16] x86/pci: Add Hygon Dhyana support to PCI and north bridge
Date: Wed, 19 Sep 2018 17:20:03 +0000	[thread overview]
Message-ID: <d05c7aa5-05ba-5ac2-c70f-414d9539925f@amd.com> (raw)
In-Reply-To: <035e5d0a4f2a0edf68ca0f1019e47b878eaa5da6.1536550550.git.puwen@hygon.cn>

On 09/10/2018 08:17 AM, Pu Wen wrote:
> As Hygon registered its PCI Vendor ID as a new one 0x1d94, and there
> are PCI Devices 0x1450/0x1463/0x1464 for Host bridge on Hygon Dhyana
> platforms, so add Hygon Dhyana support to the PCI and north bridge
> subsystem by using the code path of AMD family 17h.
> 
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# pci_ids.h
> Signed-off-by: Pu Wen <puwen@hygon.cn>
> ---
>  arch/x86/kernel/amd_nb.c | 47 +++++++++++++++++++++++++++++++++++++++++------
>  arch/x86/pci/amd_bus.c   |  6 ++++--
>  include/linux/pci_ids.h  |  2 ++
>  3 files changed, 47 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
> index b481b95..3e2ea18 100644
> --- a/arch/x86/kernel/amd_nb.c
> +++ b/arch/x86/kernel/amd_nb.c
> @@ -61,6 +61,21 @@ static const struct pci_device_id amd_nb_link_ids[] = {
>  	{}
>  };
>  
> +static const struct pci_device_id hygon_root_ids[] = {
> +	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
> +	{}
> +};
> +
> +const struct pci_device_id hygon_nb_misc_ids[] = {
> +	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
> +	{}
> +};
> +
> +static const struct pci_device_id hygon_nb_link_ids[] = {
> +	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
> +	{}
> +};
> +
>  const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
>  	{ 0x00, 0x18, 0x20 },
>  	{ 0xff, 0x00, 0x20 },
> @@ -197,12 +212,25 @@ int amd_cache_northbridges(void)
>  	u16 i = 0;
>  	struct amd_northbridge *nb;
>  	struct pci_dev *root, *misc, *link;
> +	const struct pci_device_id *root_ids = NULL;
> +	const struct pci_device_id *misc_ids = NULL;
> +	const struct pci_device_id *link_ids = NULL;
> +
> +	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
> +		root_ids = amd_root_ids;
> +		misc_ids = amd_nb_misc_ids;
> +		link_ids = amd_nb_link_ids;
> +	} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
> +		root_ids = hygon_root_ids;
> +		misc_ids = hygon_nb_misc_ids;
> +		link_ids = hygon_nb_link_ids;
> +	}

To be compatible with "before this patch" you should probably do:

	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
		root_ids = hygon_root_ids;
		misc_ids = hygon_nb_misc_ids;
		link_ids = hygon_nb_link_ids;
	} else {
		root_ids = amd_root_ids;
		misc_ids = amd_nb_misc_ids;
		link_ids = amd_nb_link_ids;
	}

That way they are always the AMD values if not your chip.

>  
>  	if (amd_northbridges.num)
>  		return 0;
>  
>  	misc = NULL;
> -	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
> +	while ((misc = next_northbridge(misc, misc_ids)) != NULL)
>  		i++;
>  
>  	if (!i)
> @@ -218,11 +246,11 @@ int amd_cache_northbridges(void)
>  	link = misc = root = NULL;
>  	for (i = 0; i != amd_northbridges.num; i++) {
>  		node_to_amd_nb(i)->root = root =
> -			next_northbridge(root, amd_root_ids);
> +			next_northbridge(root, root_ids);
>  		node_to_amd_nb(i)->misc = misc =
> -			next_northbridge(misc, amd_nb_misc_ids);
> +			next_northbridge(misc, misc_ids);
>  		node_to_amd_nb(i)->link = link =
> -			next_northbridge(link, amd_nb_link_ids);
> +			next_northbridge(link, link_ids);
>  	}
>  
>  	if (amd_gart_present())
> @@ -263,9 +291,15 @@ bool __init early_is_amd_nb(u32 device)
>  {
>  	const struct pci_device_id *id;
>  	u32 vendor = device & 0xffff;
> +	const struct pci_device_id *misc_ids = NULL;
> +
> +	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> +		misc_ids = amd_nb_misc_ids;
> +	else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
> +		misc_ids = hygon_nb_misc_ids;

Same comment as above.  This will probably eliminate the PANIC that
that was reported by LKP.

Thanks,
Tom

>  
>  	device >>= 16;
> -	for (id = amd_nb_misc_ids; id->vendor; id++)
> +	for (id = misc_ids; id->vendor; id++)
>  		if (vendor == id->vendor && device == id->device)
>  			return true;
>  	return false;
> @@ -277,7 +311,8 @@ struct resource *amd_get_mmconfig_range(struct resource *res)
>  	u64 base, msr;
>  	unsigned int segn_busn_bits;
>  
> -	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
> +	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
>  		return NULL;
>  
>  	/* assume all cpus from fam10h have mmconfig */
> diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
> index 649bdde..bfa50e6 100644
> --- a/arch/x86/pci/amd_bus.c
> +++ b/arch/x86/pci/amd_bus.c
> @@ -93,7 +93,8 @@ static int __init early_root_info_init(void)
>  		vendor = id & 0xffff;
>  		device = (id>>16) & 0xffff;
>  
> -		if (vendor != PCI_VENDOR_ID_AMD)
> +		if (vendor != PCI_VENDOR_ID_AMD &&
> +		    vendor != PCI_VENDOR_ID_HYGON)
>  			continue;
>  
>  		if (hb_probes[i].device == device) {
> @@ -390,7 +391,8 @@ static int __init pci_io_ecs_init(void)
>  
>  static int __init amd_postcore_init(void)
>  {
> -	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
> +	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
>  		return 0;
>  
>  	early_root_info_init();
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index d157983..8a0841c 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2561,6 +2561,8 @@
>  
>  #define PCI_VENDOR_ID_AMAZON		0x1d0f
>  
> +#define PCI_VENDOR_ID_HYGON		0x1d94
> +
>  #define PCI_VENDOR_ID_TEKRAM		0x1de1
>  #define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
>  
> 

  parent reply	other threads:[~2018-09-19 17:20 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-10 13:15 [PATCH v6 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-09-10 13:15 ` [PATCH v6 01/16] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2018-09-10 16:38   ` Borislav Petkov
2018-09-11  6:33     ` Pu Wen
2018-09-10 13:15 ` [PATCH v6 02/16] x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana Pu Wen
2018-09-10 13:16 ` [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Pu Wen
2018-09-10 18:06   ` Borislav Petkov
2018-09-11  6:39     ` Pu Wen
2018-09-10 13:16 ` [PATCH v6 04/16] x86/smpboot: SMP init nodelay and not flush caches before sleep Pu Wen
2018-09-10 13:16 ` [PATCH v6 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure Pu Wen
2018-09-10 18:17   ` Borislav Petkov
2018-09-11  7:00     ` Pu Wen
2018-09-10 13:16 ` [PATCH v6 06/16] x86/alternative: Init ideal_nops for Hygon Dhyana Pu Wen
2018-09-10 13:17 ` [PATCH v6 07/16] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-11 10:07   ` Borislav Petkov
2018-09-19 17:20   ` Lendacky, Thomas [this message]
2018-09-20  7:25     ` Thomas Gleixner
2018-09-20  8:05     ` Pu Wen
2018-09-10 13:17 ` [PATCH v6 08/16] x86/apic: Add Hygon Dhyana support to APIC Pu Wen
2018-09-11 10:14   ` Borislav Petkov
2018-09-11 13:03     ` Pu Wen
2018-09-10 13:17 ` [PATCH v6 09/16] x86/bugs: Add mitigation to spectre and no meltdown for Hygon Dhyana Pu Wen
2018-09-11 10:38   ` Borislav Petkov
2018-09-11 13:17     ` Pu Wen
2018-09-10 13:17 ` [PATCH v6 10/16] x86/mce: Add Hygon Dhyana support to MCE infrastructure Pu Wen
2018-09-11 10:43   ` Borislav Petkov
2018-09-10 13:18 ` [PATCH v6 11/16] x86/kvm: Add Hygon Dhyana support to KVM infrastructure Pu Wen
2018-09-10 13:19 ` [PATCH v6 12/16] x86/xen: Add Hygon Dhyana support to Xen Pu Wen
2018-09-10 13:19 ` [PATCH v6 13/16] ACPI, x86: Add Hygon Dhyana support Pu Wen
2018-09-10 13:20 ` [PATCH v6 14/16] cpufreq, " Pu Wen
2018-09-10 13:20 ` [PATCH v6 15/16] EDAC, amd64: " Pu Wen
2018-09-11 10:51   ` Borislav Petkov
2018-09-10 13:20 ` [PATCH v6 16/16] cpupower, x86: " Pu Wen
2018-10-01 19:38   ` Shuah Khan
2018-10-04  1:21     ` [RESEND PATCH v8 16/16] cpupower: " Pu Wen
2018-10-04  8:03       ` [tip:x86/cpu] tools/cpupower: " tip-bot for Pu Wen
2018-09-23  9:30 [PATCH v8 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-09-23  9:33 ` [PATCH v8 01/16] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2018-09-27 17:00   ` [tip:x86/cpu] " tip-bot for Pu Wen
2018-09-23  9:33 ` [PATCH v8 02/16] x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana Pu Wen
2018-09-27 17:01   ` [tip:x86/cpu] " tip-bot for Pu Wen
2018-09-23  9:34 ` [PATCH v8 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Pu Wen
2018-09-27 17:02   ` [tip:x86/cpu] " tip-bot for Pu Wen
2018-09-23  9:34 ` [PATCH v8 04/16] x86/smpboot: SMP init no delay and not flush caches before sleep Pu Wen
2018-09-27 17:02   ` [tip:x86/cpu] x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana tip-bot for Pu Wen
2018-09-23  9:34 ` [PATCH v8 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure Pu Wen
2018-09-27 17:03   ` [tip:x86/cpu] x86/events: " tip-bot for Pu Wen
2018-09-23  9:35 ` [PATCH v8 06/16] x86/alternative: Init ideal_nops for Hygon Dhyana Pu Wen
2018-09-27 17:03   ` [tip:x86/cpu] " tip-bot for Pu Wen
2018-09-23  9:35 ` [PATCH v8 07/16] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-23 11:10   ` Borislav Petkov
2018-09-23 12:54     ` Pu Wen
2018-09-24 15:24   ` Borislav Petkov
2018-09-25 12:27     ` Pu Wen
2018-09-25 12:30       ` Borislav Petkov
2018-09-25 12:57         ` Pu Wen
2018-09-25 14:45     ` [PATCH 1/2] x86/amd_nb: Add vendor checking for strict function access Pu Wen
2018-09-27 17:04       ` [tip:x86/cpu] x86/amd_nb: Check vendor in AMD-only functions tip-bot for Pu Wen
2018-09-25 14:46     ` [PATCH 2/2] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-27 17:04       ` [tip:x86/cpu] x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge tip-bot for Pu Wen
2018-09-23  9:35 ` [PATCH v8 08/16] x86/apic: Add Hygon Dhyana support to APIC Pu Wen
2018-09-27 17:05   ` [tip:x86/cpu] x86/apic: Add Hygon Dhyana support tip-bot for Pu Wen
2018-09-23  9:35 ` [PATCH v8 09/16] x86/bugs: Add mitigation to spectre and no meltdown for Hygon Dhyana Pu Wen
2018-09-27 17:06   ` [tip:x86/cpu] x86/bugs: Add Hygon Dhyana to the respective mitigation machinery tip-bot for Pu Wen
2018-09-23  9:36 ` [PATCH v8 10/16] x86/mce: Add Hygon Dhyana support to MCE infrastructure Pu Wen
2018-09-27 17:06   ` [tip:x86/cpu] x86/mce: Add Hygon Dhyana support to the MCA infrastructure tip-bot for Pu Wen
2018-09-23  9:36 ` [PATCH v8 11/16] x86/kvm: Add Hygon Dhyana support to KVM infrastructure Pu Wen
2018-09-27 17:07   ` [tip:x86/cpu] x86/kvm: Add Hygon Dhyana support to KVM tip-bot for Pu Wen
2018-09-23  9:36 ` [PATCH v8 12/16] x86/xen: Add Hygon Dhyana support to Xen Pu Wen
2018-09-27 17:07   ` [tip:x86/cpu] " tip-bot for Pu Wen
2018-09-23  9:37 ` [PATCH v8 13/16] ACPI, x86: Add Hygon Dhyana support Pu Wen
2018-09-27 17:08   ` [tip:x86/cpu] ACPI: " tip-bot for Pu Wen
2018-09-23  9:37 ` [PATCH v8 14/16] cpufreq, x86: " Pu Wen
2018-09-27 17:08   ` [tip:x86/cpu] cpufreq: " tip-bot for Pu Wen
2018-09-23  9:37 ` [PATCH v8 15/16] EDAC, amd64: " Pu Wen
2018-09-23  9:38 ` [PATCH v8 16/16] cpupower, x86: " Pu Wen

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